Makefile

   1 GHDL=ghdl
   2 GHDLFLAGS=--std=08 -Psim-unisim
   3 CFLAGS=-O2 -Wall
   4
   5 all = core_tb simple_ram_behavioural_tb soc_reset_tb icache_tb multiply_tb dmi_dtm_tb divider_tb \
   6         rotator_tb countzero_tb
   7
   8 # XXX
   9 # loadstore_tb fetch_tb
  10
  11 all: $(all)
  12
  13 %.o : %.vhdl
  14         $(GHDL) -a $(GHDLFLAGS) $<
  15
  16 common.o: decode_types.o
  17 control.o: gpr_hazard.o
  18 sim_jtag.o: sim_jtag_socket.o
  19 core_tb.o: common.o wishbone_types.o core.o soc.o sim_jtag.o
  20 core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o core_debug.o divider.o
  21 core_debug.o: common.o
  22 countzero.o:
  23 countzero_tb.o: common.o glibc_random.o countzero.o
  24 cr_file.o: common.o
  25 crhelpers.o: common.o
  26 decode1.o: common.o decode_types.o
  27 decode2.o: decode_types.o common.o helpers.o insn_helpers.o control.o
  28 decode_types.o:
  29 execute1.o: decode_types.o common.o helpers.o crhelpers.o insn_helpers.o ppc_fx_insns.o rotator.o logical.o countzero.o
  30 execute2.o: common.o crhelpers.o ppc_fx_insns.o
  31 fetch1.o: common.o
  32 fetch2.o: common.o wishbone_types.o
  33 glibc_random_helpers.o:
  34 glibc_random.o: glibc_random_helpers.o
  35 helpers.o:
  36 cache_ram.o:
  37 plru.o:
  38 plru_tb.o: plru.o
  39 icache.o: common.o wishbone_types.o plru.o cache_ram.o
  40 icache_tb.o: common.o wishbone_types.o icache.o simple_ram_behavioural.o
  41 insn_helpers.o:
  42 loadstore1.o: common.o helpers.o
  43 loadstore2.o: common.o helpers.o wishbone_types.o
  44 logical.o: decode_types.o
  45 multiply_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o multiply.o
  46 multiply.o: common.o decode_types.o ppc_fx_insns.o crhelpers.o
  47 divider_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o divider.o
  48 divider.o: common.o decode_types.o crhelpers.o
  49 ppc_fx_insns.o: helpers.o
  50 register_file.o: common.o
  51 rotator.o: common.o
  52 rotator_tb.o: common.o glibc_random.o ppc_fx_insns.o insn_helpers.o rotator.o
  53 sim_console.o:
  54 simple_ram_behavioural_helpers.o:
  55 simple_ram_behavioural_tb.o: wishbone_types.o simple_ram_behavioural.o
  56 simple_ram_behavioural.o: wishbone_types.o simple_ram_behavioural_helpers.o
  57 sim_uart.o: wishbone_types.o sim_console.o
  58 soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o simple_ram_behavioural.o dmi_dtm_xilinx.o wishbone_debug_master.o
  59 wishbone_arbiter.o: wishbone_types.o
  60 wishbone_types.o:
  61 writeback.o: common.o
  62 dmi_dtm_tb.o: dmi_dtm_xilinx.o wishbone_debug_master.o
  63 dmi_dtm_xilinx.o: wishbone_types.o sim-unisim/unisim_vcomponents.o
  64 wishbone_debug_master.o: wishbone_types.o
  65
  66 UNISIM_BITS = sim-unisim/unisim_vcomponents.vhdl sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl
  67 sim-unisim/unisim_vcomponents.o: $(UNISIM_BITS)
  68         $(GHDL) -a $(GHDLFLAGS) --work=unisim --workdir=sim-unisim $^
  69
  70
  71 fpga/soc_reset_tb.o: fpga/soc_reset.o
  72
  73 soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
  74         $(GHDL) -e $(GHDLFLAGS) soc_reset_tb
  75
  76 core_tb: core_tb.o simple_ram_behavioural_helpers_c.o sim_console_c.o sim_jtag_socket_c.o
  77         $(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o $@
  78
  79 fetch_tb: fetch_tb.o
  80         $(GHDL) -e $(GHDLFLAGS) $@
  81
  82 icache_tb: icache_tb.o
  83         $(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
  84
  85 plru_tb: plru_tb.o
  86         $(GHDL) -e $(GHDLFLAGS) $@
  87
  88 loadstore_tb: loadstore_tb.o
  89         $(GHDL) -e $(GHDLFLAGS) $@
  90
  91 multiply_tb: multiply_tb.o
  92         $(GHDL) -e $(GHDLFLAGS) $@
  93
  94 divider_tb: divider_tb.o
  95         $(GHDL) -e $(GHDLFLAGS) $@
  96
  97 rotator_tb: rotator_tb.o
  98         $(GHDL) -e $(GHDLFLAGS) $@
  99
 100 countzero_tb: countzero_tb.o
 101         $(GHDL) -e $(GHDLFLAGS) $@
 102
 103 simple_ram_tb: simple_ram_tb.o
 104         $(GHDL) -e $(GHDLFLAGS) $@
 105
 106 simple_ram_behavioural_tb: simple_ram_behavioural_helpers_c.o simple_ram_behavioural_tb.o
 107         $(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
 108
 109 dmi_dtm_tb: dmi_dtm_tb.o simple_ram_behavioural_helpers_c.o
 110         $(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
 111
 112 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 113
 114 check: $(tests) test_micropython test_micropython_long
 115
 116 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long
 117
 118 $(tests): core_tb
 119         @./scripts/run_test.sh $@
 120
 121 test_micropython: core_tb
 122         @./scripts/test_micropython.py
 123
 124 test_micropython_long: core_tb
 125         @./scripts/test_micropython_long.py
 126
 127 clean:
 128         rm -f *.o work-*cf unisim-*cf $(all)
 129         rm -f sim-unisim/*.o sim-unisim/unisim-*cf
 130
 131 distclean: clean
 132         rm -f *~ fpga/~