Makefile

   1 GHDL=ghdl
   2 GHDLFLAGS=--std=08 -Psim-unisim
   3 CFLAGS=-O2 -Wall
   4
   5 all = core_tb soc_reset_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
   6         rotator_tb countzero_tb wishbone_bram_tb
   7
   8 # XXX
   9 # loadstore_tb fetch_tb
  10
  11 all: $(all)
  12
  13 %.o : %.vhdl
  14         $(GHDL) -a $(GHDLFLAGS) --workdir=$(shell dirname $@) $<
  15
  16 common.o: decode_types.o
  17 control.o: gpr_hazard.o cr_hazard.o common.o
  18 sim_jtag.o: sim_jtag_socket.o
  19 core_tb.o: common.o wishbone_types.o core.o soc.o sim_jtag.o
  20 core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o loadstore1.o dcache.o multiply.o writeback.o core_debug.o divider.o
  21 core_debug.o: common.o
  22 countzero.o:
  23 countzero_tb.o: common.o glibc_random.o countzero.o
  24 cr_file.o: common.o
  25 crhelpers.o: common.o
  26 decode1.o: common.o decode_types.o
  27 decode2.o: decode_types.o common.o helpers.o insn_helpers.o control.o
  28 decode_types.o:
  29 execute1.o: decode_types.o common.o helpers.o crhelpers.o insn_helpers.o ppc_fx_insns.o rotator.o logical.o countzero.o
  30 fetch1.o: common.o
  31 fetch2.o: common.o wishbone_types.o
  32 glibc_random_helpers.o:
  33 glibc_random.o: glibc_random_helpers.o
  34 helpers.o:
  35 cache_ram.o:
  36 plru.o:
  37 plru_tb.o: plru.o
  38 utils.o:
  39 sim_bram.o: sim_bram_helpers.o utils.o
  40 wishbone_bram_wrapper.o: wishbone_types.o sim_bram.o utils.o
  41 wishbone_bram_tb.o: wishbone_bram_wrapper.o
  42 icache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
  43 icache_tb.o: common.o wishbone_types.o icache.o wishbone_bram_wrapper.o
  44 dcache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
  45 dcache_tb.o: common.o wishbone_types.o dcache.o wishbone_bram_wrapper.o
  46 insn_helpers.o:
  47 loadstore1.o: common.o helpers.o
  48 logical.o: decode_types.o
  49 multiply_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o multiply.o
  50 multiply.o: common.o decode_types.o
  51 divider_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o divider.o
  52 divider.o: common.o decode_types.o
  53 ppc_fx_insns.o: helpers.o
  54 register_file.o: common.o
  55 rotator.o: common.o
  56 rotator_tb.o: common.o glibc_random.o ppc_fx_insns.o insn_helpers.o rotator.o
  57 sim_console.o:
  58 sim_uart.o: wishbone_types.o sim_console.o
  59 soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o wishbone_bram_wrapper.o dmi_dtm_xilinx.o wishbone_debug_master.o
  60 wishbone_arbiter.o: wishbone_types.o
  61 wishbone_types.o:
  62 writeback.o: common.o crhelpers.o
  63 dmi_dtm_tb.o: dmi_dtm_xilinx.o wishbone_debug_master.o
  64 dmi_dtm_xilinx.o: wishbone_types.o sim-unisim/unisim_vcomponents.o
  65 wishbone_debug_master.o: wishbone_types.o
  66
  67 UNISIM_BITS = sim-unisim/unisim_vcomponents.vhdl sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl
  68 sim-unisim/unisim_vcomponents.o: $(UNISIM_BITS)
  69         $(GHDL) -a $(GHDLFLAGS) --work=unisim --workdir=sim-unisim $^
  70
  71
  72 fpga/soc_reset_tb.o: fpga/soc_reset.o
  73
  74 soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
  75         $(GHDL) -e $(GHDLFLAGS) --workdir=fpga soc_reset_tb
  76
  77 core_tb: core_tb.o sim_bram_helpers_c.o sim_console_c.o sim_jtag_socket_c.o
  78         $(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o $@
  79
  80 fetch_tb: fetch_tb.o
  81         $(GHDL) -e $(GHDLFLAGS) $@
  82
  83 icache_tb: icache_tb.o
  84         $(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@
  85
  86 dcache_tb: dcache_tb.o
  87         $(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@
  88
  89 plru_tb: plru_tb.o
  90         $(GHDL) -e $(GHDLFLAGS) $@
  91
  92 loadstore_tb: loadstore_tb.o
  93         $(GHDL) -e $(GHDLFLAGS) $@
  94
  95 multiply_tb: multiply_tb.o
  96         $(GHDL) -e $(GHDLFLAGS) $@
  97
  98 divider_tb: divider_tb.o
  99         $(GHDL) -e $(GHDLFLAGS) $@
 100
 101 rotator_tb: rotator_tb.o
 102         $(GHDL) -e $(GHDLFLAGS) $@
 103
 104 countzero_tb: countzero_tb.o
 105         $(GHDL) -e $(GHDLFLAGS) $@
 106
 107 simple_ram_tb: simple_ram_tb.o
 108         $(GHDL) -e $(GHDLFLAGS) $@
 109
 110 wishbone_bram_tb: sim_bram_helpers_c.o wishbone_bram_tb.o
 111         $(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@
 112
 113 dmi_dtm_tb: dmi_dtm_tb.o sim_bram_helpers_c.o
 114         $(GHDL) -e $(GHDLFLAGS) -Wl,sim_bram_helpers_c.o $@
 115
 116 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 117
 118 check: $(tests) test_micropython test_micropython_long
 119
 120 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long
 121
 122 $(tests): core_tb
 123         @./scripts/run_test.sh $@
 124
 125 test_micropython: core_tb
 126         @./scripts/test_micropython.py
 127
 128 test_micropython_long: core_tb
 129         @./scripts/test_micropython_long.py
 130
 131 clean:
 132         rm -f *.o work-*cf unisim-*cf $(all)
 133         rm -f fpga/*.o fpga/work-*cf
 134         rm -f sim-unisim/*.o sim-unisim/unisim-*cf
 135
 136 distclean: clean
 137         rm -f *~ fpga/~