1 ### Makefile for the cclass project
6 WORKING_DIR
:= $(shell pwd
)
8 BSVINCDIR
:= .
:%/Prelude
:%/Libraries
:%/Libraries
/BlueNoC
:.
/bsv_src
9 default
: gen_pinmux gen_verilog
12 @if
test -z
"$$BLUESPECDIR"; then echo
"BLUESPECDIR variable not set"; exit
1; fi
;
14 ###### Setting the variables for bluespec compile #$############################
15 BSVCOMPILEOPTS
:= -check-assert
-suppress-warnings G0020
-keep-fires
-opt-undetermined-vals
-remove-false-rules
-remove-empty-rules
-remove-starved-rules
16 BSVLINKOPTS
:=-parallel-sim-link
8 -keep-fires
17 VERILOGDIR
:=.
/verilog
/
18 BSVBUILDDIR
:=.
/bsv_build
/
20 ################################################################################
22 ########## BSIM COMPILE, LINK AND SIMULATE TARGETS #################################
25 @if
[ "$(define_macros)" != "$(old_define_macros)" ]; then make
clean ; fi
;
29 @python .
/src
/pinmux_generator.py
32 gen_verilog
: check-restore check-blue
33 @echo Compiling mkTbSoc in Verilog for simulations ...
34 @mkdir
-p
$(BSVBUILDDIR
);
35 @mkdir
-p
$(VERILOGDIR
);
36 bsc
-u
-verilog
-elab
-vdir
$(VERILOGDIR
) -bdir
$(BSVBUILDDIR
) -info-dir
$(BSVBUILDDIR
) $(define_macros
) -D verilog
=True
$(BSVCOMPILEOPTS
) -verilog-filter
${BLUESPECDIR}/bin
/basicinout
-p
$(BSVINCDIR
) -g
$(TOP_MODULE
) $(TOP_DIR
)/$(TOP_FILE
) 2>&1 | tee bsv_compile.log
37 @echo Compilation finished
39 ########################################################################################
43 rm -rf
$(BSVBUILDDIR
) *.log
$(BSVOUTDIR
) .
/bbl
* verilog obj_dir bsv_src src
/*.pyc