5 # It takes forever to build with optimisation, so disable by default
10 NEXTPNR ?
= nextpnr-ecp5
14 # We need a version of GHDL built with either the LLVM or gcc backend.
15 # Fedora provides this, but other distros may not. Another option is to use
30 ifeq ($(USE_DOCKER
), 1)
32 DOCKERARGS
= run
--rm -v
$(PWD
):/src
:z
-w
/src
33 GHDL
= $(DOCKERBIN
) $(DOCKERARGS
) ghdl
/ghdl
:buster-llvm-7 ghdl
34 CC
= $(DOCKERBIN
) $(DOCKERARGS
) ghdl
/ghdl
:buster-llvm-7 gcc
36 YOSYS
= $(DOCKERBIN
) $(DOCKERARGS
) hdlc
/ghdl
:yosys yosys
37 NEXTPNR
= $(DOCKERBIN
) $(DOCKERARGS
) hdlc
/nextpnr
:ecp5 nextpnr-ecp5
38 ECPPACK
= $(DOCKERBIN
) $(DOCKERARGS
) hdlc
/prjtrellis ecppack
39 OPENOCD
= $(DOCKERBIN
) $(DOCKERARGS
) --device
/dev
/bus
/usb hdlc
/prog openocd
42 all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
43 rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
47 core_files
= decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
48 utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
49 decode1.vhdl helpers.vhdl insn_helpers.vhdl \
50 control.vhdl decode2.vhdl register_file.vhdl \
51 cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
52 logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
53 loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
56 soc_files
= wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
57 wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
58 spi_rxtx.vhdl spi_flash_ctrl.vhdl
60 uart_files
= $(wildcard uart16550
/*.v
)
62 soc_sim_files
= $(core_files
) $(soc_files
) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
63 sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
65 random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl
67 soc_sim_c_files
= sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
70 soc_sim_obj_files
=$(soc_sim_c_files
:.c
=.o
)
72 soc_sim_link
=$(patsubst %,-Wl
$(comma
)%,$(soc_sim_obj_files
))
74 unisim_dir
= sim-unisim
75 unisim_lib
= $(unisim_dir
)/unisim-obj08.cf
76 unisim_lib_files
= $(unisim_dir
)/BSCANE2.vhdl
$(unisim_dir
)/BUFG.vhdl \
77 $(unisim_dir
)/unisim_vcomponents.vhdl
78 $(unisim_lib
): $(unisim_lib_files
)
79 $(GHDL
) -i
--std
=08 --work
=unisim
--workdir
=$(unisim_dir
) $^
80 GHDLFLAGS
+= -P
$(unisim_dir
)
82 core_tbs
= multiply_tb divider_tb rotator_tb countzero_tb
83 soc_tbs
= core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
84 soc_flash_tbs
= core_flash_tb
85 soc_dram_tbs
= dram_tb core_dram_tb
87 ifneq ($(FLASH_MODEL_PATH
),)
88 fmf_dir
= $(FLASH_MODEL_PATH
)/fmf
89 fmf_lib
= $(fmf_dir
)/fmf-obj08.cf
90 fmf_lib_files
= $(wildcard $(fmf_dir
)/*.vhd
)
91 GHDLFLAGS
+= -P
$(fmf_dir
)
92 $(fmf_lib
): $(fmf_lib_files
)
93 $(GHDL
) -i
--std
=08 --work
=fmf
--workdir
=$(fmf_dir
) $^
95 flash_model_files
=$(FLASH_MODEL_PATH
)/s25fl128s.vhd
96 flash_model_files
: $(fmf_lib
)
98 flash_model_files
=sim_no_flash.vhdl
102 $(soc_flash_tbs
): %: $(soc_sim_files
) $(soc_sim_obj_files
) $(unisim_lib
) $(fmf_lib
) $(flash_model_files
) %.vhdl
103 $(GHDL
) -c
$(GHDLFLAGS
) $(soc_sim_link
) $(soc_sim_files
) $(flash_model_files
) $@.vhdl
$(unisim_files
) -e
$@
105 $(soc_tbs
): %: $(soc_sim_files
) $(soc_sim_obj_files
) $(unisim_lib
) %.vhdl
106 $(GHDL
) -c
$(GHDLFLAGS
) $(soc_sim_link
) $(soc_sim_files
) $@.vhdl
-e
$@
108 $(core_tbs
): %: $(core_files
) glibc_random.vhdl glibc_random_helpers.vhdl
%.vhdl
109 $(GHDL
) -c
$(GHDLFLAGS
) $(core_files
) glibc_random.vhdl glibc_random_helpers.vhdl
$@.vhdl
-e
$@
111 soc_reset_tb
: fpga
/soc_reset_tb.vhdl fpga
/soc_reset.vhdl
112 $(GHDL
) -c
$(GHDLFLAGS
) fpga
/soc_reset_tb.vhdl fpga
/soc_reset.vhdl
-e
$@
115 VERILATOR_ROOT
=$(shell verilator
-getenv VERILATOR_ROOT
2>/dev
/null
)
116 ifeq (, $(VERILATOR_ROOT
))
118 $(error
"Verilator is required to make this target !")
121 verilated_dram
: litedram
/generated
/sim
/litedram_core.v
122 verilator
$(VERILATOR_FLAGS
) -CFLAGS
$(VERILATOR_CFLAGS
) -Wno-fatal
--cc $< --trace
123 make
-C obj_dir
-f ..
/litedram
/extras
/sim_dram_verilate.mk VERILATOR_ROOT
=$(VERILATOR_ROOT
)
125 SIM_DRAM_CFLAGS
= -I.
-Iobj_dir
-Ilitedram
/generated
/sim
-I
$(VERILATOR_ROOT
)/include -I
$(VERILATOR_ROOT
)/include/vltstd
126 SIM_DRAM_CFLAGS
+= -DVM_COVERAGE
=0 -DVM_SC
=0 -DVM_TRACE
=1 -DVL_PRINTF
=printf
-faligned-new
127 sim_litedram_c.o
: litedram
/extras
/sim_litedram_c.
cpp verilated_dram
128 $(CC
) $(CPPFLAGS
) $(SIM_DRAM_CFLAGS
) $(CFLAGS
) -c
$< -o
$@
130 soc_dram_files
= $(core_files
) $(soc_files
) litedram
/extras
/litedram-wrapper-l2.vhdl litedram
/generated
/sim
/litedram-initmem.vhdl
131 soc_dram_sim_files
= $(soc_sim_files
) litedram
/extras
/sim_litedram.vhdl
132 soc_dram_sim_obj_files
= $(soc_sim_obj_files
) sim_litedram_c.o
133 dram_link_files
=-Wl
,obj_dir
/Vlitedram_core__ALL.a
-Wl
,obj_dir
/verilated.o
-Wl
,obj_dir
/verilated_vcd_c.o
-Wl
,-lstdc
++
134 soc_dram_sim_link
=$(patsubst %,-Wl
$(comma
)%,$(soc_dram_sim_obj_files
)) $(dram_link_files
)
136 $(soc_dram_tbs
): %: $(soc_dram_files
) $(soc_dram_sim_files
) $(soc_dram_sim_obj_files
) $(flash_model_files
) $(unisim_lib
) $(fmf_lib
) %.vhdl
137 $(GHDL
) -c
$(GHDLFLAGS
) $(soc_dram_sim_link
) $(soc_dram_files
) $(soc_dram_sim_files
) $(flash_model_files
) $@.vhdl
-e
$@
142 RAM_INIT_FILE
=hello_world
/hello_world.hex
146 #RAM_INIT_FILE=micropython/firmware.hex
148 FPGA_TARGET ?
= ORANGE-CRAB
150 # OrangeCrab with ECP85
151 ifeq ($(FPGA_TARGET
), ORANGE-CRAB
)
154 CLK_FREQUENCY
=40000000
155 LPF
=constraints
/orange-crab.lpf
157 NEXTPNR_FLAGS
=--um5g-85k
--freq
40
158 OPENOCD_JTAG_CONFIG
=openocd
/olimex-arm-usb-tiny-h.cfg
159 OPENOCD_DEVICE_CONFIG
=openocd
/LFE5UM5G-85F.cfg
163 ifeq ($(FPGA_TARGET
), ECP5-EVN
)
166 CLK_FREQUENCY
=40000000
167 LPF
=constraints
/ecp5-evn.lpf
169 NEXTPNR_FLAGS
=--um5g-85k
--freq
40
170 OPENOCD_JTAG_CONFIG
=openocd
/ecp5-evn.cfg
171 OPENOCD_DEVICE_CONFIG
=openocd
/LFE5UM5G-85F.cfg
174 GHDL_IMAGE_GENERICS
=-gMEMORY_SIZE
=$(MEMORY_SIZE
) -gRAM_INIT_FILE
=$(RAM_INIT_FILE
) \
175 -gRESET_LOW
=$(RESET_LOW
) -gCLK_INPUT
=$(CLK_INPUT
) -gCLK_FREQUENCY
=$(CLK_FREQUENCY
)
177 clkgen
=fpga
/clk_gen_ecp5.vhd
178 toplevel
=fpga
/top-generic.vhdl
179 dmi_dtm
=dmi_dtm_dummy.vhdl
181 ifeq ($(FPGA_TARGET
), verilator
)
184 CLK_FREQUENCY
=50000000
185 clkgen
=fpga
/clk_gen_bypass.vhd
188 fpga_files
= fpga
/soc_reset.vhdl \
189 fpga
/pp_fifo.vhd fpga
/pp_soc_uart.vhd fpga
/main_bram.vhdl \
192 synth_files
= $(core_files
) $(soc_files
) $(fpga_files
) $(clkgen
) $(toplevel
) $(dmi_dtm
)
194 microwatt.json
: $(synth_files
) $(RAM_INIT_FILE
)
195 $(YOSYS
) -m
$(GHDLSYNTH
) -p
"ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files
)
197 microwatt.v
: $(synth_files
) $(RAM_INIT_FILE
)
198 $(YOSYS
) -m
$(GHDLSYNTH
) -p
"ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
200 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
201 microwatt-verilator
: microwatt.v verilator
/microwatt-verilator.
cpp verilator
/uart-verilator.c
202 verilator
$(VERILATOR_FLAGS
) -CFLAGS
"$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert
--cc $< --exe verilator
/microwatt-verilator.
cpp verilator
/uart-verilator.c
-o
$@
-Iuart16550
-Wno-fatal
-Wno-CASEOVERLAP
-Wno-UNOPTFLAT
#--trace
203 make
-C obj_dir
-f Vmicrowatt.mk
204 @cp
-f obj_dir
/microwatt-verilator microwatt-verilator
206 microwatt_out.config
: microwatt.json
$(LPF
)
207 $(NEXTPNR
) --json
$< --lpf
$(LPF
) --textcfg
$@.tmp
$(NEXTPNR_FLAGS
) --package
$(PACKAGE
)
210 microwatt.bit
: microwatt_out.config
211 $(ECPPACK
) --svf microwatt.svf
$< $@
213 microwatt.svf
: microwatt.bit
216 $(OPENOCD
) -f
$(OPENOCD_JTAG_CONFIG
) -f
$(OPENOCD_DEVICE_CONFIG
) -c
"transport select jtag; init; svf $<; exit"
218 tests
= $(sort $(patsubst tests
/%.out
,%,$(wildcard tests
/*.out
)))
219 tests_console
= $(sort $(patsubst tests
/%.console_out
,%,$(wildcard tests
/*.console_out
)))
221 tests_console
: $(tests_console
)
223 check: $(tests
) tests_console test_micropython test_micropython_long tests_unit
225 check_light
: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
228 @.
/scripts
/run_test.sh
$@
230 $(tests_console
): core_tb
231 @.
/scripts
/run_test_console.sh
$@
233 test_micropython
: core_tb
234 @.
/scripts
/test_micropython.py
236 test_micropython_long
: core_tb
237 @.
/scripts
/test_micropython_long.py
239 tests_core_tb
= $(patsubst %_tb
,%_tb_test
,$(core_tbs
))
240 tests_soc_tb
= $(patsubst %_tb
,%_tb_test
,$(soc_tbs
))
243 .
/$< --assert-level
=error
> /dev
/null
245 tests_core
: $(tests_core_tb
)
247 tests_soc
: $(tests_soc_tb
)
249 # FIXME SOC tests have bit rotted, so disable for now
250 #tests_unit: tests_core tests_soc
251 tests_unit
: tests_core
254 find .
-name
'*.vhdl' | xargs .
/scripts
/vhdltags
259 rm -f
*.o
*.cf
$(all)
260 rm -f fpga
/*.o fpga
/*.cf
261 rm -f sim-unisim
/*.o sim-unisim
/*.cf
262 rm -f litedram
/extras
/*.o
264 rm -f scripts
/mw_debug
/*.o
265 rm -f scripts
/mw_debug
/mw_debug
266 rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
267 rm -f microwatt.v microwatt-verilator
271 make
-f scripts
/mw_debug
/Makefile
clean
272 make
-f hello_world
/Makefile
clean
275 rm -f
*~ fpga
/*~ lib
/*~ console
/*~
include/*~
276 rm -rf litedram
/build
277 rm -f litedram
/extras
/*~
278 rm -f litedram
/gen-src
/*~
279 rm -f litedram
/gen-src
/sdram_init
/*~
280 make
-f scripts
/mw_debug
/Makefile
distclean
281 make
-f hello_world
/Makefile
distclean
283 .PHONY
: all prog
check check_light
clean distclean
284 .PRECIOUS
: microwatt.json microwatt_out.config microwatt.bit