Makefile

   1 GHDL=ghdl
   2 GHDLFLAGS=--std=08 -Psim-unisim
   3 CFLAGS=-O2 -Wall
   4
   5 all = core_tb simple_ram_behavioural_tb soc_reset_tb icache_tb multiply_tb dmi_dtm_tb
   6
   7 # XXX
   8 # loadstore_tb fetch_tb
   9
  10 all: $(all)
  11
  12 %.o : %.vhdl
  13         $(GHDL) -a $(GHDLFLAGS) $<
  14
  15 common.o: decode_types.o
  16 core_tb.o: common.o core.o soc.o
  17 core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o
  18 cr_file.o: common.o
  19 crhelpers.o: common.o
  20 decode1.o: common.o decode_types.o
  21 decode2.o: decode_types.o common.o helpers.o insn_helpers.o
  22 decode_types.o:
  23 execute1.o: decode_types.o common.o helpers.o crhelpers.o ppc_fx_insns.o
  24 execute2.o: common.o crhelpers.o ppc_fx_insns.o
  25 fetch1.o: common.o
  26 fetch2.o: common.o wishbone_types.o
  27 glibc_random_helpers.o:
  28 glibc_random.o: glibc_random_helpers.o
  29 helpers.o:
  30 icache.o: common.o wishbone_types.o
  31 icache_tb.o: common.o wishbone_types.o icache.o simple_ram_behavioural.o
  32 insn_helpers.o:
  33 loadstore1.o: common.o
  34 loadstore2.o: common.o helpers.o wishbone_types.o
  35 multiply_tb.o: common.o glibc_random.o ppc_fx_insns.o multiply.o
  36 multiply.o: common.o decode_types.o ppc_fx_insns.o crhelpers.o
  37 ppc_fx_insns.o: helpers.o
  38 register_file.o: common.o
  39 sim_console.o:
  40 simple_ram_behavioural_helpers.o:
  41 simple_ram_behavioural_tb.o: wishbone_types.o simple_ram_behavioural.o
  42 simple_ram_behavioural.o: wishbone_types.o simple_ram_behavioural_helpers.o
  43 sim_uart.o: wishbone_types.o sim_console.o
  44 soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o simple_ram_behavioural.o dmi_dtm_xilinx.o wishbone_debug_master.o
  45 wishbone_arbiter.o: wishbone_types.o
  46 wishbone_types.o:
  47 writeback.o: common.o
  48 dmi_dtm_tb.o: dmi_dtm_xilinx.o wishbone_debug_master.o
  49 dmi_dtm_xilinx.o: sim-unisim/unisim_vcomponents.o
  50 wishbone_debug_master.o: wishbone_types.o
  51
  52 UNISIM_BITS = sim-unisim/unisim_vcomponents.vhdl sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl
  53 sim-unisim/unisim_vcomponents.o: $(UNISIM_BITS)
  54         $(GHDL) -a $(GHDLFLAGS) --work=unisim --workdir=sim-unisim $^
  55
  56
  57 fpga/soc_reset_tb.o: fpga/soc_reset.o
  58
  59 soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
  60         $(GHDL) -e $(GHDLFLAGS) soc_reset_tb
  61
  62 core_tb: core_tb.o simple_ram_behavioural_helpers_c.o sim_console_c.o
  63         $(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o -Wl,sim_console_c.o $@
  64
  65 fetch_tb: fetch_tb.o
  66         $(GHDL) -e $(GHDLFLAGS) $@
  67
  68 icache_tb: icache_tb.o
  69         $(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
  70
  71 loadstore_tb: loadstore_tb.o
  72         $(GHDL) -e $(GHDLFLAGS) $@
  73
  74 multiply_tb: multiply_tb.o
  75         $(GHDL) -e $(GHDLFLAGS) $@
  76
  77 simple_ram_tb: simple_ram_tb.o
  78         $(GHDL) -e $(GHDLFLAGS) $@
  79
  80 simple_ram_behavioural_tb: simple_ram_behavioural_helpers_c.o simple_ram_behavioural_tb.o
  81         $(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
  82
  83 dmi_dtm_tb: dmi_dtm_tb.o simple_ram_behavioural_helpers_c.o
  84         $(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@
  85
  86 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
  87
  88 check: $(tests) test_micropython test_micropython_long
  89
  90 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long
  91
  92 $(tests): core_tb
  93         @./scripts/run_test.sh $@
  94
  95 test_micropython: core_tb
  96         @./scripts/test_micropython.py
  97
  98 test_micropython_long: core_tb
  99         @./scripts/test_micropython_long.py
 100
 101 clean:
 102         rm -f *.o work-*cf unisim-*cf $(all)
 103         rm -f sim-unisim/*.o sim-unisim/unisim-*cf