Makefile

   1 GHDL ?= ghdl
   2 GHDLFLAGS=--std=08 -frelaxed
   3 CFLAGS=-O3 -Wall
   4
   5 GHDLSYNTH ?= ghdl.so
   6 YOSYS     ?= yosys
   7 NEXTPNR   ?= nextpnr-ecp5
   8 ECPPACK   ?= ecppack
   9 OPENOCD   ?= openocd
  10
  11 # We need a version of GHDL built with either the LLVM or gcc backend.
  12 # Fedora provides this, but other distros may not. Another option is to use
  13 # the Docker image.
  14 DOCKER ?= 0
  15 PODMAN ?= 0
  16
  17 ifeq ($(DOCKER), 1)
  18 DOCKERBIN=docker
  19 USE_DOCKER=1
  20 endif
  21
  22 ifeq ($(PODMAN), 1)
  23 DOCKERBIN=podman
  24 USE_DOCKER=1
  25 endif
  26
  27 ifeq ($(USE_DOCKER), 1)
  28 PWD = $(shell pwd)
  29 DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
  30 GHDL      = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
  31 CC        = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
  32 GHDLSYNTH = ghdl
  33 YOSYS     = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:beta yosys
  34 NEXTPNR   = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:nextpnr-ecp5 nextpnr-ecp5
  35 ECPPACK   = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:trellis ecppack
  36 OPENOCD   = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb ghdl/synth:prog openocd
  37 endif
  38
  39 all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
  40         rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
  41
  42 all: $(all)
  43
  44 core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
  45         utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
  46         decode1.vhdl helpers.vhdl insn_helpers.vhdl gpr_hazard.vhdl \
  47         cr_hazard.vhdl control.vhdl decode2.vhdl register_file.vhdl \
  48         cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
  49         logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
  50         loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
  51         core.vhdl
  52
  53 soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
  54         wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
  55         spi_rxtx.vhdl spi_flash_ctrl.vhdl
  56
  57
  58 soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
  59         sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
  60         sim_16550_uart.vhdl
  61
  62 soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
  63         sim_jtag_socket_c.c
  64
  65 soc_sim_obj_files=$(soc_sim_c_files:.c=.o)
  66 comma := ,
  67 soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files))
  68
  69 unisim_dir = sim-unisim
  70 unisim_lib = $(unisim_dir)/unisim-obj08.cf
  71 unisim_lib_files = $(unisim_dir)/BSCANE2.vhdl $(unisim_dir)/BUFG.vhdl \
  72         $(unisim_dir)/unisim_vcomponents.vhdl
  73 $(unisim_lib): $(unisim_lib_files)
  74         ghdl -i --std=08 --work=unisim --workdir=$(unisim_dir) $^
  75 GHDLFLAGS += -P$(unisim_dir)
  76
  77 core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
  78 soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
  79 soc_flash_tbs = core_flash_tb
  80 soc_dram_tbs = dram_tb core_dram_tb
  81
  82 ifneq ($(FLASH_MODEL_PATH),)
  83 fmf_dir = $(FLASH_MODEL_PATH)/fmf
  84 fmf_lib = $(fmf_dir)/fmf-obj08.cf
  85 fmf_lib_files = $(wildcard $(fmf_dir)/*.vhd)
  86 GHDLFLAGS += -P$(fmf_dir)
  87 $(fmf_lib): $(fmf_lib_files)
  88         ghdl -i --std=08 --work=fmf --workdir=$(fmf_dir) $^
  89
  90 flash_model_files=$(FLASH_MODEL_PATH)/s25fl128s.vhd
  91 flash_model_files: $(fmf_lib)
  92 else
  93 flash_model_files=sim_no_flash.vhdl
  94 fmf_lib=
  95 endif
  96
  97 $(soc_flash_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) $(fmf_lib) $(flash_model_files) %.vhdl
  98         $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $(flash_model_files) $@.vhdl $(unisim_files) -e $@
  99
 100 $(soc_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) %.vhdl
 101         $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $@.vhdl -e $@
 102
 103 $(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
 104         $(GHDL) -c $(GHDLFLAGS) $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
 105
 106 soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
 107         $(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
 108
 109 # LiteDRAM sim
 110 VERILATOR_ROOT=$(shell verilator -getenv VERILATOR_ROOT 2>/dev/null)
 111 ifeq (, $(VERILATOR_ROOT))
 112 $(soc_dram_tbs):
 113         $(error "Verilator is required to make this target !")
 114 else
 115
 116 VERILATOR_CFLAGS=-O3
 117 VERILATOR_FLAGS=-O3
 118 verilated_dram: litedram/generated/sim/litedram_core.v
 119         verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
 120         make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
 121
 122 SIM_DRAM_CFLAGS  = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
 123 SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -faligned-new
 124 sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
 125         $(CC)  $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
 126
 127 soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
 128 soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
 129 soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
 130 dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
 131 soc_dram_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_dram_sim_obj_files)) $(dram_link_files)
 132
 133 $(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) $(flash_model_files) $(unisim_lib) $(fmf_lib) %.vhdl
 134         $(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(soc_dram_files) $(soc_dram_sim_files) $(flash_model_files) $@.vhdl -e $@
 135 endif
 136
 137 # Hello world
 138 MEMORY_SIZE=8192
 139 RAM_INIT_FILE=hello_world/hello_world.hex
 140
 141 # Micropython
 142 #MEMORY_SIZE=393216
 143 #RAM_INIT_FILE=micropython/firmware.hex
 144
 145 # OrangeCrab with ECP85
 146 RESET_LOW=true
 147 CLK_INPUT=50000000
 148 CLK_FREQUENCY=50000000
 149 LPF=constraints/orange-crab.lpf
 150 PACKAGE=CSFBGA285
 151 NEXTPNR_FLAGS=--um5g-85k --freq 50
 152 OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
 153 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 154
 155 # ECP5-EVN
 156 #RESET_LOW=true
 157 #CLK_INPUT=12000000
 158 #CLK_FREQUENCY=12000000
 159 #LPF=constraints/ecp5-evn.lpf
 160 #PACKAGE=CABGA381
 161 #NEXTPNR_FLAGS=--um5g-85k --freq 12
 162 #OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 163 #OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 164
 165 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
 166         -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
 167
 168 clkgen=fpga/clk_gen_bypass.vhd
 169 toplevel=fpga/top-generic.vhdl
 170 dmi_dtm=dmi_dtm_dummy.vhdl
 171
 172 fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
 173         fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl
 174
 175 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 176
 177 microwatt.json: $(synth_files)
 178         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@"
 179
 180 microwatt.v: $(synth_files)
 181         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 182
 183 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 184 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
 185         verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
 186         make -C obj_dir -f Vmicrowatt.mk
 187         @cp -f obj_dir/microwatt-verilator microwatt-verilator
 188
 189 microwatt_out.config: microwatt.json $(LPF)
 190         $(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@.tmp $(NEXTPNR_FLAGS) --package $(PACKAGE)
 191         mv -f $@.tmp $@
 192
 193 microwatt.bit: microwatt_out.config
 194         $(ECPPACK) --svf microwatt.svf $< $@
 195
 196 microwatt.svf: microwatt.bit
 197
 198 prog: microwatt.svf
 199         $(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
 200
 201 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 202 tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
 203
 204 tests_console: $(tests_console)
 205
 206 check: $(tests) tests_console test_micropython test_micropython_long tests_unit
 207
 208 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
 209
 210 $(tests): core_tb
 211         @./scripts/run_test.sh $@
 212
 213 $(tests_console): core_tb
 214         @./scripts/run_test_console.sh $@
 215
 216 test_micropython: core_tb
 217         @./scripts/test_micropython.py
 218
 219 test_micropython_long: core_tb
 220         @./scripts/test_micropython_long.py
 221
 222 tests_core_tb = $(patsubst %_tb,%_tb_test,$(core_tbs))
 223 tests_soc_tb = $(patsubst %_tb,%_tb_test,$(soc_tbs))
 224
 225 %_test: %
 226         ./$< --assert-level=error > /dev/null
 227
 228 tests_core: $(tests_core_tb)
 229
 230 tests_soc: $(tests_soc_tb)
 231
 232 # FIXME SOC tests have bit rotted, so disable for now
 233 #tests_unit: tests_core tests_soc
 234 tests_unit: tests_core
 235
 236 TAGS:
 237         find . -name '*.vhdl' | xargs ./scripts/vhdltags
 238
 239 .PHONY: TAGS
 240
 241 _clean:
 242         rm -f *.o *.cf $(all)
 243         rm -f fpga/*.o fpga/*.cf
 244         rm -f sim-unisim/*.o sim-unisim/*.cf
 245         rm -f litedram/extras/*.o
 246         rm -f TAGS
 247         rm -f scripts/mw_debug/*.o
 248         rm -f scripts/mw_debug/mw_debug
 249         rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
 250         rm -f microwatt.v microwatt-verilator
 251         rm -rf obj_dir/
 252
 253 clean: _clean
 254         make -f scripts/mw_debug/Makefile clean
 255         make -f hello_world/Makefile clean
 256
 257 distclean: _clean
 258         rm -f *~ fpga/*~ lib/*~ console/*~ include/*~
 259         rm -rf litedram/build
 260         rm -f litedram/extras/*~
 261         rm -f litedram/gen-src/*~
 262         rm -f litedram/gen-src/sdram_init/*~
 263         make -f scripts/mw_debug/Makefile distclean
 264         make -f hello_world/Makefile distclean
 265
 266 .PHONY: all prog check check_light clean distclean
 267 .PRECIOUS: microwatt.json microwatt_out.config microwatt.bit