Makefile

   1 GHDL ?= ghdl
   2 GHDLFLAGS=--std=08 --work=unisim
   3 CFLAGS=-O2 -Wall
   4
   5 GHDLSYNTH ?= ghdl.so
   6 YOSYS     ?= yosys
   7 NEXTPNR   ?= nextpnr-ecp5
   8 ECPPACK   ?= ecppack
   9 OPENOCD   ?= openocd
  10
  11 # We need a version of GHDL built with either the LLVM or gcc backend.
  12 # Fedora provides this, but other distros may not. Another option is to use
  13 # the Docker image.
  14 DOCKER ?= 0
  15 PODMAN ?= 0
  16
  17 ifeq ($(DOCKER), 1)
  18 DOCKERBIN=docker
  19 USE_DOCKER=1
  20 endif
  21
  22 ifeq ($(PODMAN), 1)
  23 DOCKERBIN=podman
  24 USE_DOCKER=1
  25 endif
  26
  27 ifeq ($(USE_DOCKER), 1)
  28 PWD = $(shell pwd)
  29 DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
  30 GHDL      = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
  31 CC        = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
  32 GHDLSYNTH = ghdl
  33 YOSYS     = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:beta yosys
  34 NEXTPNR   = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:nextpnr-ecp5 nextpnr-ecp5
  35 ECPPACK   = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:trellis ecppack
  36 OPENOCD   = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb ghdl/synth:prog openocd
  37 endif
  38
  39 all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
  40         rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
  41
  42 all: $(all)
  43
  44 core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
  45         fetch2.vhdl utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
  46         decode1.vhdl helpers.vhdl insn_helpers.vhdl gpr_hazard.vhdl \
  47         cr_hazard.vhdl control.vhdl decode2.vhdl register_file.vhdl \
  48         cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
  49         logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
  50         loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
  51         core.vhdl
  52
  53 soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl \
  54         wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl
  55
  56 soc_sim_files = sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \
  57         sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl \
  58         sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl \
  59         sim-unisim/unisim_vcomponents.vhdl dmi_dtm_xilinx.vhdl
  60
  61 soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
  62         sim_jtag_socket_c.c
  63 soc_sim_obj_files=$(soc_sim_c_files:.c=.o)
  64 comma := ,
  65 soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files))
  66
  67 core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
  68 soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
  69
  70 $(soc_tbs): %: $(core_files) $(soc_files) $(soc_sim_files) $(soc_sim_obj_files) %.vhdl
  71         $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(core_files) $(soc_files) $(soc_sim_files) $@.vhdl -e $@
  72
  73 $(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
  74         $(GHDL) -c $(GHDLFLAGS) $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
  75
  76 soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
  77         $(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
  78
  79 # Hello world
  80 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=8192 -gRAM_INIT_FILE=hello_world/hello_world.hex
  81
  82 # Micropython
  83 #GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=393216 -gRAM_INIT_FILE=micropython/firmware.hex
  84
  85 # OrangeCrab with ECP85
  86 GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=50000000 -gCLK_FREQUENCY=50000000
  87 LPF=constraints/orange-crab.lpf
  88 PACKAGE=CSFBGA285
  89 NEXTPNR_FLAGS=--um5g-85k --freq 50
  90 OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
  91 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
  92
  93 # ECP5-EVN
  94 #GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=12000000 -gCLK_FREQUENCY=12000000
  95 #LPF=constraints/ecp5-evn.lpf
  96 #PACKAGE=CABGA381
  97 #NEXTPNR_FLAGS=--um5g-85k --freq 12
  98 #OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
  99 #OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 100
 101 clkgen=fpga/clk_gen_bypass.vhd
 102 toplevel=fpga/top-generic.vhdl
 103 dmi_dtm=dmi_dtm_dummy.vhdl
 104
 105 fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
 106         fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl
 107
 108 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 109
 110 microwatt.json: $(synth_files)
 111         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@"
 112
 113 microwatt.v: $(synth_files)
 114         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 115
 116 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 117 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
 118         verilator -O3 --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
 119         make -C obj_dir -f Vmicrowatt.mk
 120         @cp -f obj_dir/microwatt-verilator microwatt-verilator
 121
 122 microwatt_out.config: microwatt.json $(LPF)
 123         $(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)
 124
 125 microwatt.bit: microwatt_out.config
 126         $(ECPPACK) --svf microwatt.svf $< $@
 127
 128 microwatt.svf: microwatt.bit
 129
 130 prog: microwatt.svf
 131         $(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
 132
 133 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 134 tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
 135
 136 check: $(tests) $(tests_console) test_micropython test_micropython_long
 137
 138 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long $(tests_console)
 139
 140 $(tests): core_tb
 141         @./scripts/run_test.sh $@
 142
 143 $(tests_console): core_tb
 144         @./scripts/run_test_console.sh $@
 145
 146 test_micropython: core_tb
 147         @./scripts/test_micropython.py
 148
 149 test_micropython_long: core_tb
 150         @./scripts/test_micropython_long.py
 151
 152 TAGS:
 153         find . -name '*.vhdl' | xargs ./scripts/vhdltags
 154
 155 .PHONY: TAGS
 156
 157 _clean:
 158         rm -f *.o work-*cf unisim-*cf $(all)
 159         rm -f fpga/*.o fpga/work-*cf
 160         rm -f sim-unisim/*.o sim-unisim/unisim-*cf
 161         rm -f TAGS
 162         rm -f scripts/mw_debug/*.o
 163         rm -f scripts/mw_debug/mw_debug
 164         rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
 165         rm -f microwatt.v microwatt-verilator
 166         rm -rf obj_dir/
 167
 168 clean: _clean
 169         make -f scripts/mw_debug/Makefile clean
 170         make -f hello_world/Makefile clean
 171
 172 distclean: _clean
 173         rm -f *~ fpga/*~ lib/*~ console/*~ include/*~
 174         rm -rf litedram/build
 175         rm -f litedram/extras/*~
 176         rm -f litedram/gen-src/*~
 177         rm -f litedram/gen-src/sdram_init/*~
 178         make -f scripts/mw_debug/Makefile distclean
 179         make -f hello_world/Makefile distclean
 180
 181 .PHONY: all prog check check_light clean distclean
 182 .PRECIOUS: microwatt.json microwatt_out.config microwatt.bit