Makefile

   1 GHDL=ghdl
   2 GHDLFLAGS=--std=08 -Psim-unisim
   3 CFLAGS=-O2 -Wall
   4
   5 # We need a version of GHDL built with either the LLVM or gcc backend.
   6 # Fedora provides this, but other distros may not. Another option, although
   7 # rather slow, is to use the Docker image.
   8 #
   9 # Uncomment one of these to build with Docker or podman
  10 #DOCKER=docker
  11 #DOCKER=podman
  12 #
  13 # Uncomment these lines to build with Docker/podman
  14 #PWD = $(shell pwd)
  15 #DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
  16 #GHDL = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
  17 #CC = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
  18
  19 all = core_tb soc_reset_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
  20         rotator_tb countzero_tb wishbone_bram_tb
  21
  22 # XXX
  23 # loadstore_tb fetch_tb
  24
  25 all: $(all)
  26
  27 %.o : %.vhdl
  28         $(GHDL) -a $(GHDLFLAGS) --workdir=$(shell dirname $@) $<
  29
  30 common.o: decode_types.o
  31 control.o: gpr_hazard.o cr_hazard.o common.o
  32 sim_jtag.o: sim_jtag_socket.o
  33 core_tb.o: common.o wishbone_types.o core.o soc.o sim_jtag.o
  34 core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o loadstore1.o dcache.o writeback.o core_debug.o
  35 core_debug.o: common.o
  36 countzero.o:
  37 countzero_tb.o: common.o glibc_random.o countzero.o
  38 cr_file.o: common.o
  39 crhelpers.o: common.o
  40 decode1.o: common.o decode_types.o
  41 decode2.o: decode_types.o common.o helpers.o insn_helpers.o control.o
  42 decode_types.o:
  43 execute1.o: decode_types.o common.o helpers.o crhelpers.o insn_helpers.o ppc_fx_insns.o rotator.o logical.o countzero.o multiply.o divider.o
  44 fetch1.o: common.o
  45 fetch2.o: common.o wishbone_types.o
  46 glibc_random_helpers.o:
  47 glibc_random.o: glibc_random_helpers.o
  48 helpers.o:
  49 cache_ram.o:
  50 plru.o:
  51 plru_tb.o: plru.o
  52 utils.o:
  53 sim_bram.o: sim_bram_helpers.o utils.o
  54 wishbone_bram_wrapper.o: wishbone_types.o sim_bram.o utils.o
  55 wishbone_bram_tb.o: wishbone_bram_wrapper.o
  56 icache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
  57 icache_tb.o: common.o wishbone_types.o icache.o wishbone_bram_wrapper.o
  58 dcache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
  59 dcache_tb.o: common.o wishbone_types.o dcache.o wishbone_bram_wrapper.o
  60 insn_helpers.o:
  61 loadstore1.o: common.o helpers.o
  62 logical.o: decode_types.o
  63 multiply_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o multiply.o
  64 multiply.o: common.o decode_types.o
  65 divider_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o divider.o
  66 divider.o: common.o decode_types.o
  67 ppc_fx_insns.o: helpers.o
  68 register_file.o: common.o
  69 rotator.o: common.o
  70 rotator_tb.o: common.o glibc_random.o ppc_fx_insns.o insn_helpers.o rotator.o
  71 sim_console.o:
  72 sim_uart.o: wishbone_types.o sim_console.o
  73 soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o wishbone_bram_wrapper.o dmi_dtm_xilinx.o wishbone_debug_master.o
  74 wishbone_arbiter.o: wishbone_types.o
  75 wishbone_types.o:
  76 writeback.o: common.o crhelpers.o
  77 dmi_dtm_tb.o: dmi_dtm_xilinx.o wishbone_debug_master.o
  78 dmi_dtm_xilinx.o: wishbone_types.o sim-unisim/unisim_vcomponents.o
  79 wishbone_debug_master.o: wishbone_types.o
  80
  81 UNISIM_BITS = sim-unisim/unisim_vcomponents.vhdl sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl
  82 sim-unisim/unisim_vcomponents.o: $(UNISIM_BITS)
  83         $(GHDL) -a $(GHDLFLAGS) --work=unisim --workdir=sim-unisim $^
  84
  85
  86 fpga/soc_reset_tb.o: fpga/soc_reset.o
  87
  88 soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
  89         $(GHDL) -e $(GHDLFLAGS) --workdir=fpga soc_reset_tb
  90
  91 core_tb: core_tb.o sim_vhpi_c.o sim_bram_helpers_c.o sim_console_c.o sim_jtag_socket_c.o
  92         $(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o $@
  93
  94 fetch_tb: fetch_tb.o
  95         $(GHDL) -e $(GHDLFLAGS) $@
  96
  97 icache_tb: icache_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
  98         $(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
  99
 100 dcache_tb: dcache_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
 101         $(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
 102
 103 plru_tb: plru_tb.o
 104         $(GHDL) -e $(GHDLFLAGS) $@
 105
 106 loadstore_tb: loadstore_tb.o
 107         $(GHDL) -e $(GHDLFLAGS) $@
 108
 109 multiply_tb: multiply_tb.o
 110         $(GHDL) -e $(GHDLFLAGS) $@
 111
 112 divider_tb: divider_tb.o
 113         $(GHDL) -e $(GHDLFLAGS) $@
 114
 115 rotator_tb: rotator_tb.o
 116         $(GHDL) -e $(GHDLFLAGS) $@
 117
 118 countzero_tb: countzero_tb.o
 119         $(GHDL) -e $(GHDLFLAGS) $@
 120
 121 simple_ram_tb: simple_ram_tb.o
 122         $(GHDL) -e $(GHDLFLAGS) $@
 123
 124 wishbone_bram_tb: sim_vhpi_c.o sim_bram_helpers_c.o wishbone_bram_tb.o
 125         $(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
 126
 127 dmi_dtm_tb: dmi_dtm_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
 128         $(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
 129
 130 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 131
 132 check: $(tests) test_micropython test_micropython_long
 133
 134 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long
 135
 136 $(tests): core_tb
 137         @./scripts/run_test.sh $@
 138
 139 test_micropython: core_tb
 140         @./scripts/test_micropython.py
 141
 142 test_micropython_long: core_tb
 143         @./scripts/test_micropython_long.py
 144
 145 clean:
 146         rm -f *.o work-*cf unisim-*cf $(all)
 147         rm -f fpga/*.o fpga/work-*cf
 148         rm -f sim-unisim/*.o sim-unisim/unisim-*cf
 149
 150 distclean: clean
 151         rm -f *~ fpga/~