Makefile

   1 GHDL ?= ghdl
   2 GHDLFLAGS=--std=08 --work=unisim -frelaxed
   3 CFLAGS=-O3 -Wall
   4
   5 GHDLSYNTH ?= ghdl.so
   6 YOSYS     ?= yosys
   7 NEXTPNR   ?= nextpnr-ecp5
   8 ECPPACK   ?= ecppack
   9 OPENOCD   ?= openocd
  10
  11 # We need a version of GHDL built with either the LLVM or gcc backend.
  12 # Fedora provides this, but other distros may not. Another option is to use
  13 # the Docker image.
  14 DOCKER ?= 0
  15 PODMAN ?= 0
  16
  17 ifeq ($(DOCKER), 1)
  18 DOCKERBIN=docker
  19 USE_DOCKER=1
  20 endif
  21
  22 ifeq ($(PODMAN), 1)
  23 DOCKERBIN=podman
  24 USE_DOCKER=1
  25 endif
  26
  27 ifeq ($(USE_DOCKER), 1)
  28 PWD = $(shell pwd)
  29 DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
  30 GHDL      = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
  31 CC        = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
  32 GHDLSYNTH = ghdl
  33 YOSYS     = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:beta yosys
  34 NEXTPNR   = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:nextpnr-ecp5 nextpnr-ecp5
  35 ECPPACK   = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:trellis ecppack
  36 OPENOCD   = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb ghdl/synth:prog openocd
  37 endif
  38
  39 all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
  40         rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
  41
  42 all: $(all)
  43
  44 core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
  45         fetch2.vhdl utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
  46         decode1.vhdl helpers.vhdl insn_helpers.vhdl gpr_hazard.vhdl \
  47         cr_hazard.vhdl control.vhdl decode2.vhdl register_file.vhdl \
  48         cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
  49         logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
  50         loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
  51         core.vhdl
  52
  53 soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
  54         wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl
  55
  56 soc_sim_files = sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \
  57         sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl \
  58         sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl \
  59         sim-unisim/unisim_vcomponents.vhdl dmi_dtm_xilinx.vhdl
  60
  61 soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
  62         sim_jtag_socket_c.c
  63 soc_sim_obj_files=$(soc_sim_c_files:.c=.o)
  64 comma := ,
  65 soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files))
  66
  67 core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
  68 soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
  69 soc_dram_tbs = dram_tb core_dram_tb
  70
  71 $(soc_tbs): %: $(core_files) $(soc_files) $(soc_sim_files) $(soc_sim_obj_files) %.vhdl
  72         $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(core_files) $(soc_files) $(soc_sim_files) $@.vhdl -e $@
  73
  74 $(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
  75         $(GHDL) -c $(GHDLFLAGS) $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
  76
  77 soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
  78         $(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
  79
  80 # LiteDRAM sim
  81 VERILATOR_ROOT=$(shell verilator -getenv VERILATOR_ROOT 2>/dev/null)
  82 ifeq (, $(VERILATOR_ROOT))
  83 $(soc_dram_tbs):
  84         $(error "Verilator is required to make this target !")
  85 else
  86
  87 VERILATOR_CFLAGS=-O3
  88 VERILATOR_FLAGS=-O3
  89 verilated_dram: litedram/generated/sim/litedram_core.v
  90         verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
  91         make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
  92
  93 SIM_DRAM_CFLAGS  = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
  94 SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -faligned-new
  95 sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
  96         $(CC)  $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
  97
  98 soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
  99 soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
 100 soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
 101 dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
 102 soc_dram_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_dram_sim_obj_files)) $(dram_link_files)
 103
 104 $(soc_dram_tbs): %: $(core_files) $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) %.vhdl
 105         $(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(core_files) $(soc_dram_files) $(soc_dram_sim_files) $@.vhdl -e $@
 106 endif
 107
 108 # Hello world
 109 MEMORY_SIZE=8192
 110 RAM_INIT_FILE=hello_world/hello_world.hex
 111
 112 # Micropython
 113 #MEMORY_SIZE=393216
 114 #RAM_INIT_FILE=micropython/firmware.hex
 115
 116 # OrangeCrab with ECP85
 117 RESET_LOW=true
 118 CLK_INPUT=50000000
 119 CLK_FREQUENCY=50000000
 120 LPF=constraints/orange-crab.lpf
 121 PACKAGE=CSFBGA285
 122 NEXTPNR_FLAGS=--um5g-85k --freq 50
 123 OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
 124 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 125
 126 # ECP5-EVN
 127 #RESET_LOW=true
 128 #CLK_INPUT=12000000
 129 #CLK_FREQUENCY=12000000
 130 #LPF=constraints/ecp5-evn.lpf
 131 #PACKAGE=CABGA381
 132 #NEXTPNR_FLAGS=--um5g-85k --freq 12
 133 #OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 134 #OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 135
 136 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
 137         -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
 138
 139 clkgen=fpga/clk_gen_bypass.vhd
 140 toplevel=fpga/top-generic.vhdl
 141 dmi_dtm=dmi_dtm_dummy.vhdl
 142
 143 fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
 144         fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl
 145
 146 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 147
 148 microwatt.json: $(synth_files)
 149         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@"
 150
 151 microwatt.v: $(synth_files)
 152         $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 153
 154 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 155 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
 156         verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
 157         make -C obj_dir -f Vmicrowatt.mk
 158         @cp -f obj_dir/microwatt-verilator microwatt-verilator
 159
 160 microwatt_out.config: microwatt.json $(LPF)
 161         $(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)
 162
 163 microwatt.bit: microwatt_out.config
 164         $(ECPPACK) --svf microwatt.svf $< $@
 165
 166 microwatt.svf: microwatt.bit
 167
 168 prog: microwatt.svf
 169         $(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
 170
 171 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 172 tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
 173
 174 tests_console: $(tests_console)
 175
 176 check: $(tests) tests_console test_micropython test_micropython_long tests_unit
 177
 178 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
 179
 180 $(tests): core_tb
 181         @./scripts/run_test.sh $@
 182
 183 $(tests_console): core_tb
 184         @./scripts/run_test_console.sh $@
 185
 186 test_micropython: core_tb
 187         @./scripts/test_micropython.py
 188
 189 test_micropython_long: core_tb
 190         @./scripts/test_micropython_long.py
 191
 192 tests_core_tb = $(patsubst %_tb,%_tb_test,$(core_tbs))
 193 tests_soc_tb = $(patsubst %_tb,%_tb_test,$(soc_tbs))
 194
 195 %_test: %
 196         ./$< --assert-level=error > /dev/null
 197
 198 tests_core: $(tests_core_tb)
 199
 200 tests_soc: $(tests_soc_tb)
 201
 202 # FIXME SOC tests have bit rotted, so disable for now
 203 #tests_unit: tests_core tests_soc
 204 tests_unit: tests_core
 205
 206 TAGS:
 207         find . -name '*.vhdl' | xargs ./scripts/vhdltags
 208
 209 .PHONY: TAGS
 210
 211 _clean:
 212         rm -f *.o work-*cf unisim-*cf $(all)
 213         rm -f fpga/*.o fpga/work-*cf
 214         rm -f sim-unisim/*.o sim-unisim/unisim-*cf
 215         rm -f litedram/extras/*.o
 216         rm -f TAGS
 217         rm -f scripts/mw_debug/*.o
 218         rm -f scripts/mw_debug/mw_debug
 219         rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
 220         rm -f microwatt.v microwatt-verilator
 221         rm -rf obj_dir/
 222
 223 clean: _clean
 224         make -f scripts/mw_debug/Makefile clean
 225         make -f hello_world/Makefile clean
 226
 227 distclean: _clean
 228         rm -f *~ fpga/*~ lib/*~ console/*~ include/*~
 229         rm -rf litedram/build
 230         rm -f litedram/extras/*~
 231         rm -f litedram/gen-src/*~
 232         rm -f litedram/gen-src/sdram_init/*~
 233         make -f scripts/mw_debug/Makefile distclean
 234         make -f hello_world/Makefile distclean
 235
 236 .PHONY: all prog check check_light clean distclean
 237 .PRECIOUS: microwatt.json microwatt_out.config microwatt.bit