README

   1                        __   _ __      _  __
   2                       / /  (_) /____ | |/_/
   3                      / /__/ / __/ -_)>  <
   4                     /____/_/\__/\__/_/|_|
   5                          Migen inside
   6
   7                 Build your hardware, easily!
   8               Copyright 2012-2018 / EnjoyDigital
   9
  10 [> Intro
  11 --------
  12 LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
  13 our cores, integrate them in complete SoC and load/flash them to the hardware
  14 and experiment new features. (structure is kept close to MiSoC to ease
  15 collaboration)
  16
  17 Typical LiteX design flow:
  18 --------------------------
  19
  20                         +---------------+
  21                         |FPGA toolchains|
  22                         +----^-----+----+
  23                              |     |
  24                           +--+-----v--+
  25          +-------+        |           |
  26          | Migen +-------->           |
  27          +-------+        |           |        Your design
  28                           |   LiteX   +---> ready to be used!
  29                           |           |
  30 +----------------------+  |           |
  31 |LiteX Cores Ecosystem +-->           |
  32 +----------------------+  +-^-------^-+
  33  (Eth, SATA, DRAM, USB,     |       |
  34   PCIe, Video, etc...)      +       +
  35                            board   target
  36                            file    file
  37
  38
  39 [> Sub-packages
  40 ---------------
  41 gen:
  42   Provides specific or experimental modules to generate HDL that are not integrated
  43   in Migen.
  44
  45 build:
  46   Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
  47   simulate HDL code or full SoCs.
  48
  49 soc:
  50   Provides definitions/modules to build cores (bus, bank, flow), cores and tools
  51   to build a SoC from such cores.
  52
  53 boards:
  54   Provides platforms and targets for the supported boards.
  55
  56 [> Very Quick start guide (for newcomers)
  57 -----------------------------------------
  58 TimVideos.us has done an awesome job for setting up a LiteX environment easily in
  59 the litex-buildenv repo: https://github.com/timvideos/litex-buildenv
  60
  61 It's recommended for newcomers to go this way. Various FPGA boards are supported
  62 and multiple examples provided! You can even run Linux on your FPGA using LiteX
  63 very easily!
  64
  65 Migen documentation can be found here: https://m-labs.hk/migen/manual
  66
  67
  68 [> Quick start guide (for advanced users)
  69 -----------------------------------------
  70 0. If cloned from Git without the --recursive option, get the submodules:
  71   git submodule update --init
  72
  73 1. Install Python 3.5, Migen and FPGA vendor's development tools.
  74    Get Migen from: https://github.com/m-labs/migen
  75
  76 2. Compile and install binutils. Take the latest version from GNU.
  77   mkdir build && cd build
  78   ../configure --target=lm32-elf
  79   make
  80   make install
  81
  82 3. (Optional, only if you want to use a lm32 CPU in you SoC)
  83   Compile and install GCC. Take gcc-core and gcc-g++ from GNU
  84   (version 4.5 or >=4.9).
  85   rm -rf libstdc++-v3
  86   mkdir build && cd build
  87   ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
  88     --disable-libssp
  89   make
  90   make install
  91
  92 4. Build the target of your board...:
  93   Go to boards/targets and execute the target you want to build
  94
  95 5. ... and/or install Verilator and test LiteX on your computer:
  96   Download and install Verilator: http://www.veripool.org/
  97   Install libevent-devel / json-c-devel packages
  98   Go to boards/targets
  99   ./sim.py
 100
 101 6. Run a terminal program on the board's serial port at 115200 8-N-1.
 102   You should get the BIOS prompt.
 103
 104 [> Contact
 105 ----------
 106 E-mail: florent [AT] enjoy-digital.fr