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6 Copyright 2014-2015 The University of Hong Kong
8 A small footprint and configurable SATA core
9 developed for HKU by M-Labs Ltd & EnjoyDigital
13 LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
15 LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex
16 FPGA IP cores by providing simple, elegant and efficient implementations of
17 components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
19 The core uses simple and specific streaming buses and will provides in the future
20 adapters to use standardized AXI or Avalon-ST streaming buses.
22 Since Python is used to describe the HDL, the core is highly and easily
25 The synthetizable BIST can be used as a starting point to integrate SATA in
28 LiteSATA uses technologies developed in partnership with M-Labs Ltd:
29 - Migen enables generating HDL with Python in an efficient way.
30 - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
32 LiteSATA can be used as a Migen/MiSoC library (by simply installing it
33 with the provided setup.py) or can be integrated with your standard design flow
34 by generating the verilog rtl that you will use as a standard core.
39 - OOB, COMWAKE, COMINIT
40 - ALIGN inserter/remover and bytes alignment on K28.5
41 - 8B/10B encoding/decoding in transceiver
42 - Errors detection and reporting
44 - 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
47 - CONT inserter/remover
48 - Scrambling/Descrambling of data
49 - CRC inserter/checker
50 - HOLD insertion/detection
51 - Errors detection and reporting
53 - Easy to use user interfaces (Can be used with or without CPU)
54 - 48 bits sector addressing
55 - 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
56 - Errors detection and reporting
59 - Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
60 - Ports arbitration transparent to the user
63 [> Possibles improvements
64 -------------------------
65 - add standardized interfaces (AXI, Avalon-ST)
67 - add AES hardware encryption
68 - add on-the-flow compression/decompression
69 - add support for Altera PHYs.
70 - add support for Lattice PHYs.
71 - add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
73 - add Zynq Linux drivers.
74 - ... See below Support and Consulting :)
76 If you want to support these features, please contact us at florent [AT]
77 enjoy-digital.fr. You can also contact our partner on the public mailing list
78 devel [AT] lists.m-labs.hk.
82 1. Install Python3 and Xilinx's Vivado software
84 2. Obtain Migen and install it:
85 git clone https://github.com/m-labs/migen
87 python3 setup.py install
90 3. Obtain LiteScope and install it:
91 git clone https://github.com/m-labs/litescope
93 python3 setup.py install
97 git clone https://github.com/m-labs/misoc --recursive
98 XXX add setup.py to MiSoC for external use of misoclib?
101 git clone https://github.com/enjoy-digital/litesata
103 6. Build and load BIST design (only for KC705 for now):
104 python3 make.py all (-s BISTSoCDevel to add LiteScopeLA)
106 7. Test design (only for KC705 for now):
107 go to ./test directory and run:
110 8. Visualize Link Layer transactions (if BISTSoCDevel):
111 go to ./test directory and run:
112 python3 test_la.py [your_cond]
113 your_cond can be wr_cmd, id_cmd, rd_resp, ...
114 (open test_la.py to see all conditions or add yours)
116 9. If you only want to build the core and use it with your
118 python3 make.py -t core build-core
121 Simulations are available in ./lib/sata/test:
128 hdd.py is a simplified HDD model implementing all SATA layers.
129 To run a simulation, move to ./lib/sata/test and run:
133 A synthetizable BIST is provided and can be controlled with ./test/bist.py
134 By using Miscope and the provided ./test/test_link.py example you are able to
135 visualize the internal logic of the design and even inject the captured data in
140 LiteSATA is released under the very permissive two-clause BSD license. Under the
141 terms of this license, you are authorized to use LiteSATA for closed-source
143 Even though we do not require you to do so, those things are awesome, so please
145 - tell us that you are using LiteSATA
146 - cite LiteSATA in publications related to research it has helped
147 - send us feedback and suggestions for improvements
148 - send us bug reports when something goes wrong
149 - send us the modifications and improvements you have done to LiteSATA.
151 [> Support and Consulting
152 --------------------------
153 We love open-source hardware and like sharing our designs with others.
155 LiteSATA is developed and maintained by EnjoyDigital.
157 If you would like to know more about LiteSATA or if you are already a happy user
158 and would like to extend it for your needs, EnjoyDigital can provide standard
159 commercial support as well as consulting services.
161 So feel free to contact us, we'd love to work with you! (and eventually shorten
162 the list of the possible improvements :)
165 E-mail: florent [AT] enjoy-digital.fr