2 /-----------------------------------------------------------------------------\
4 | yosys -- Yosys Open SYnthesis Suite |
6 | Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> |
8 | Permission to use, copy, modify, and/or distribute this software for any |
9 | purpose with or without fee is hereby granted, provided that the above |
10 | copyright notice and this permission notice appear in all copies. |
12 | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
13 | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
14 | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
15 | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
16 | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
17 | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
18 | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
20 \-----------------------------------------------------------------------------/
23 yosys -- Yosys Open SYnthesis Suite
24 ===================================
26 This is a framework for RTL synthesis tools. It currently has
27 extensive Verilog-2005 support and provides a basic set of
28 synthesis algorithms for various application domains.
30 Yosys can be adapted to perform any synthesis job by combining
31 the existing passes (algorithms) using synthesis scripts and
32 adding additional passes as needed by extending the yosys C++
35 Yosys is free software licensed under the ISC license (a GPL
36 compatible license that is similar in terms to the MIT license
37 or the 2-clause BSD license).
43 More information and documentation can be found on the Yosys web site:
45 http://www.clifford.at/yosys/
51 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
52 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
53 TCL, readline and libffi are optional (see ENABLE_* settings in Makefile).
54 Xdot (graphviz) is used by the "show" command in yosys to display schematics.
55 For example on Ubuntu Linux 14.04 LTS the following commands will install all
56 prerequisites for building yosys:
58 $ yosys_deps="build-essential clang bison flex libreadline-dev gawk
59 tcl8.5-dev libffi-dev git mercurial graphviz xdot pkg-config"
60 $ sudo apt-get install $yosys_deps
62 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
63 as a source distribution for Visual Studio. Visit the Yosys download page for
66 http://www.clifford.at/yosys/download.html
68 To configure the build system to use a specific compiler, use one of
73 For other compilers and build configurations it might be
74 necessary to make some changes to the config section of the
80 To build Yosys simply type 'make' in this directory.
86 Note that this also downloads, builds and installs ABC (using yosys-abc
89 Yosys can be used with the interactive command shell, with
90 synthesis scripts or with command line arguments. Let's perform
91 a simple synthesis job using the interactive command shell:
96 the command "help" can be used to print a list of all available
97 commands and "help <command>" to print details on the specified command:
101 reading the design using the verilog frontend:
103 yosys> read_verilog tests/simple/fiedler-cooley.v
105 writing the design to the console in yosys's internal format:
109 elaborate design hierarchy:
113 convert processes ("always" blocks) to netlist elements and perform
114 some simple optimizations:
118 display design netlist using xdot:
122 the same thing using 'gv' as postscript viewer:
124 yosys> show -format ps -viewer gv
126 translating netlist to gate logic and perform some simple optimizations:
130 write design netlist to a new verilog file:
132 yosys> write_verilog synth.v
134 a similar synthesis can be performed using yosys command line options only:
136 $ ./yosys -o synth.v -p hierarchy -p proc -p opt \
137 -p techmap -p opt tests/simple/fiedler-cooley.v
139 or using a simple synthesis script:
142 read_verilog tests/simple/fiedler-cooley.v
143 hierarchy; proc; opt; techmap; opt
144 write_verilog synth.v
148 It is also possible to only have the synthesis commands but not the read/write
149 commands in the synthesis script:
152 hierarchy; proc; opt; techmap; opt
154 $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys
156 The following very basic synthesis script should work well with all designs:
158 # check design hierarchy
161 # translate processes (always blocks)
164 # detect and optimize FSM encodings
167 # implement memories (arrays)
170 # convert to gate logic
173 If ABC is enabled in the Yosys build configuration and a cell library is given
174 in the liberty file mycells.lib, the following synthesis script will synthesize
175 for the given cell library:
177 # the high-level stuff
178 hierarchy; proc; fsm; opt; memory; opt
180 # mapping to internal cell library
183 # mapping flip-flops to mycells.lib
184 dfflibmap -liberty mycells.lib
186 # mapping logic to mycells.lib
187 abc -liberty mycells.lib
192 If you do not have a liberty file but want to test this synthesis script,
193 you can use the file techlibs/cmos/cmos_cells.lib from the yosys sources.
195 Various more complex liberty files (for testing) can be found here:
197 http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/..
198 ../cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
199 ../cadence/lib/ami035/signalstorm/osu035_stdcells.lib
200 ../cadence/lib/tsmc018/signalstorm/osu018_stdcells.lib
201 ../cadence/lib/ami05/signalstorm/osu05_stdcells.lib
203 The command "synth" provides a good default synthesis script (see "help synth").
204 If possible a synthesis script should borrow from "synth". For example:
206 # the high-level stuff
210 # mapping to internal cells
212 dfflibmap -liberty mycells.lib
213 abc -liberty mycells.lib
216 Yosys is under construction. A more detailed documentation will follow.
219 Unsupported Verilog-2005 Features
220 =================================
222 The following Verilog-2005 features are not supported by
223 yosys and there are currently no plans to add support
226 - Non-sythesizable language features as defined in
227 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
229 - The "tri", "triand", "trior", "wand" and "wor" net types
231 - The "config" keyword and library map files
233 - The "disable", "primitive" and "specify" statements
235 - Latched logic (is synthesized as logic with feedback loops)
238 Verilog Attributes and non-standard features
239 ============================================
241 - The 'full_case' attribute on case statements is supported
242 (also the non-standard "// synopsys full_case" directive)
244 - The 'parallel_case' attribute on case statements is supported
245 (also the non-standard "// synopsys parallel_case" directive)
247 - The "// synopsys translate_off" and "// synopsys translate_on"
248 directives are also supported (but the use of `ifdef .. `endif
249 is strongly recommended instead).
251 - The "nomem2reg" attribute on modules or arrays prohibits the
252 automatic early conversion of arrays to separate registers. This
253 is potentially dangerous. Usually the front-end has good reasons
254 for converting an array to a list of registers. Prohibiting this
255 step will likely result in incorrect synthesis results.
257 - The "mem2reg" attribute on modules or arrays forces the early
258 conversion of arrays to separate registers.
260 - The "nolatches" attribute on modules or always-blocks
261 prohibits the generation of logic-loops for latches. Instead
262 all not explicitly assigned values default to x-bits. This does
263 not affect clocked storage elements such as flip-flops.
265 - The "nosync" attribute on registers prohibits the generation of a
266 storage element. The register itself will always have all bits set
267 to 'x' (undefined). The variable may only be used as blocking assigned
268 temporary variable within an always block. This is mostly used internally
269 by yosys to synthesize verilog functions and access arrays.
271 - The "blackbox" attribute on modules is used to mark empty stub modules
272 that have the same ports as the real thing but do not contain information
273 on the internal configuration. This modules are only used by the synthesis
274 passes to identify input and output ports of cells. The verilog backend
275 also does not output blackbox modules on default.
277 - The "keep" attribute on cells and wires is used to mark objects that should
278 never be removed by the optimizer. This is used for example for cells that
279 have hidden connections that are not part of the netlist, such as IO pads.
280 Setting the "keep" attribute on a module has the same effect as setting it
281 on all instances of the module.
283 - The "init" attribute on wires is set by the frontend when a register is
284 initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis
285 to add the necessary reset logic.
287 - The "top" attribute on a module marks this module as the top of the
288 design hierarchy. The "hierarchy" command sets this attribute when called
289 with "-top". Other commands, such as "flatten" and various backends
290 use this attribute to determine the top module.
292 - In addition to the (* ... *) attribute syntax, yosys supports
293 the non-standard {* ... *} attribute syntax to set default attributes
294 for everything that comes after the {* ... *} statement. (Reset
295 by adding an empty {* *} statement.)
297 - Modules can be declared with "module mod_name(...);" (with three dots
298 instead of a list of moudle ports). With this syntax it is sufficient
299 to simply declare a module port as 'input' or 'output' in the module
302 - When defining a macro with `define, all text between tripple double quotes
303 is interpreted as macro body, even if it contains unescaped newlines. The
304 tripple double quotes are removed from the macro body. For example:
306 `define MY_MACRO(a, b) """
311 - The attribute "via_celltype" can be used to implement a verilog task or
312 function by instantiating the specified cell type. The value is the name
313 of the cell type to use. For functions the name of the output port can
314 be specified by appending it to the cell type separated by a whitespace.
315 The body of the task or function is unused in this case and can be used
316 to specify a behavioral model of the cell type for simulation. For example:
318 module my_add3(A, B, C, Y);
320 input [WIDTH-1:0] A, B, C;
321 output [WIDTH-1:0] Y;
327 (* via_celltype = "my_add3 Y" *)
328 (* via_celltype_defparam_WIDTH = 32 *)
329 function [31:0] add3;
330 input [31:0] A, B, C;
338 - A limited subset of DPI-C functions is supported. The plugin mechanism
339 (see "help plugin") can be used load .so files with implementations of
340 DPI-C routines. As a non-standard extension it is possible to specify
341 a plugin alias using the "<alias>:" syntax. for example:
344 import "DPI-C" function foo:round = real my_round (real);
345 parameter real r = my_round(12.345);
348 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
350 - Sized constants (the syntax <size>'s?[bodh]<value>) support constant
351 expressions as <size>. If the expresion is not a simple identifier, it
352 must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
355 Supported features from SystemVerilog
356 =====================================
358 When read_verilog is called with -sv, it accepts some language features
361 - The "assert" statement from SystemVerilog is supported in its most basic
362 form. In module context: "assert property (<expression>);" and within an
363 always block: "assert(<expression>);". It is transformed to a $assert cell
364 that is supported by the "sat" and "write_btor" commands.
366 - The keywords "always_comb", "always_ff" and "always_latch", "logic" and
370 Roadmap / Large-scale TODOs
371 ===========================
373 - Technology mapping for real-world applications
374 - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)
376 - Implement SAT-based formal equivialence checker
377 - Write equiv pass based on hint-based register mapping
379 - Re-implement Verilog frontend (far future)
380 - cleaner (easier to use, harder to use wrong) AST format
381 - pipeline of well structured AST transformations
382 - true contextual name lookup
388 - Implement missing Verilog 2005 features:
390 - Support for real (float) const. expressions and parameters
391 - Ignore what needs to be ignored (e.g. drive and charge strengths)
392 - Check standard vs. implementation to identify missing features
394 - Miscellaneous TODO items:
396 - Add brief source code documentation to most passes and kernel code
397 - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees