README

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   5
   6                 Build your hardware, easily!
   7                 Copyright 2015 Enjoy-Digital
   8              (based on Migen/MiSoC technologies)
   9
  10 [> Intro
  11 ---------
  12 LiteX is a fork of Migen/MiSoC for our own needs at Enjoy-Digital. It provides
  13 a single python package and add some specific features to design our FPGA cores,
  14 build a SoC with or or load/flash it to the hardware.
  15
  16 The structure of LiteX is kept close to Migen/MiSoC to enable collaboration
  17 between projects.
  18
  19 [> License
  20 -----------
  21 LiteX is copyright (c) 2015 Enjoy-Digital.
  22 Since it is based on Migen/MiSoC, see gen/MIGEN_LICENSE and soc/MISOC_LICENSE or
  23 git history to get correct ownership of files.
  24
  25 [> Sub-packages
  26 -----------
  27 gen:
  28   Provides tools and simple modules to generate HDL.
  29
  30 build:
  31   Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
  32   simulate HDL code or full SoCs.
  33
  34 soc:
  35   Provides definitions/modules to build cores (bus, bank, flow), cores and tools
  36   to build a SoC from such cores.
  37
  38 boards:
  39   Provides platforms and targets for the supported boards.
  40
  41 [> Contact
  42 E-mail: florent [AT] enjoy-digital.fr