2 /-----------------------------------------------------------------------------\
4 | yosys -- Yosys Open SYnthesis Suite |
6 | Copyright (C) 2012 - 2016 Clifford Wolf <clifford@clifford.at> |
8 | Permission to use, copy, modify, and/or distribute this software for any |
9 | purpose with or without fee is hereby granted, provided that the above |
10 | copyright notice and this permission notice appear in all copies. |
12 | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
13 | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
14 | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
15 | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
16 | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
17 | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
18 | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
20 \-----------------------------------------------------------------------------/
23 yosys -- Yosys Open SYnthesis Suite
24 ===================================
26 This is a framework for RTL synthesis tools. It currently has
27 extensive Verilog-2005 support and provides a basic set of
28 synthesis algorithms for various application domains.
30 Yosys can be adapted to perform any synthesis job by combining
31 the existing passes (algorithms) using synthesis scripts and
32 adding additional passes as needed by extending the yosys C++
35 Yosys is free software licensed under the ISC license (a GPL
36 compatible license that is similar in terms to the MIT license
37 or the 2-clause BSD license).
43 More information and documentation can be found on the Yosys web site:
45 http://www.clifford.at/yosys/
51 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
52 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
53 TCL, readline and libffi are optional (see ENABLE_* settings in Makefile).
54 Xdot (graphviz) is used by the "show" command in yosys to display schematics.
55 For example on Ubuntu Linux 14.04 LTS the following commands will install all
56 prerequisites for building yosys:
58 $ yosys_deps="build-essential clang bison flex libreadline-dev gawk
59 tcl-dev libffi-dev git mercurial graphviz xdot pkg-config python3"
60 $ sudo apt-get install $yosys_deps
62 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
63 as a source distribution for Visual Studio. Visit the Yosys download page for
66 http://www.clifford.at/yosys/download.html
68 To configure the build system to use a specific compiler, use one of
73 For other compilers and build configurations it might be
74 necessary to make some changes to the config section of the
80 To build Yosys simply type 'make' in this directory.
86 Note that this also downloads, builds and installs ABC (using yosys-abc
89 Yosys can be used with the interactive command shell, with
90 synthesis scripts or with command line arguments. Let's perform
91 a simple synthesis job using the interactive command shell:
96 the command "help" can be used to print a list of all available
97 commands and "help <command>" to print details on the specified command:
101 reading the design using the Verilog frontend:
103 yosys> read_verilog tests/simple/fiedler-cooley.v
105 writing the design to the console in yosys's internal format:
109 elaborate design hierarchy:
113 convert processes ("always" blocks) to netlist elements and perform
114 some simple optimizations:
118 display design netlist using xdot:
122 the same thing using 'gv' as postscript viewer:
124 yosys> show -format ps -viewer gv
126 translating netlist to gate logic and perform some simple optimizations:
130 write design netlist to a new Verilog file:
132 yosys> write_verilog synth.v
134 a similar synthesis can be performed using yosys command line options only:
136 $ ./yosys -o synth.v -p hierarchy -p proc -p opt \
137 -p techmap -p opt tests/simple/fiedler-cooley.v
139 or using a simple synthesis script:
142 read_verilog tests/simple/fiedler-cooley.v
143 hierarchy; proc; opt; techmap; opt
144 write_verilog synth.v
148 It is also possible to only have the synthesis commands but not the read/write
149 commands in the synthesis script:
152 hierarchy; proc; opt; techmap; opt
154 $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys
156 The following very basic synthesis script should work well with all designs:
158 # check design hierarchy
161 # translate processes (always blocks)
164 # detect and optimize FSM encodings
167 # implement memories (arrays)
170 # convert to gate logic
173 If ABC is enabled in the Yosys build configuration and a cell library is given
174 in the liberty file mycells.lib, the following synthesis script will synthesize
175 for the given cell library:
177 # the high-level stuff
178 hierarchy; proc; fsm; opt; memory; opt
180 # mapping to internal cell library
183 # mapping flip-flops to mycells.lib
184 dfflibmap -liberty mycells.lib
186 # mapping logic to mycells.lib
187 abc -liberty mycells.lib
192 If you do not have a liberty file but want to test this synthesis script,
193 you can use the file examples/cmos/cmos_cells.lib from the yosys sources.
195 Liberty file downloads for and information about free and open ASIC standard
196 cell libraries can be found here:
198 http://www.vlsitechnology.org/html/libraries.html
199 http://www.vlsitechnology.org/synopsys/vsclib013.lib
201 The command "synth" provides a good default synthesis script (see "help synth").
202 If possible a synthesis script should borrow from "synth". For example:
204 # the high-level stuff
208 # mapping to internal cells
210 dfflibmap -liberty mycells.lib
211 abc -liberty mycells.lib
214 Yosys is under construction. A more detailed documentation will follow.
217 Unsupported Verilog-2005 Features
218 =================================
220 The following Verilog-2005 features are not supported by
221 yosys and there are currently no plans to add support
224 - Non-synthesizable language features as defined in
225 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
227 - The "tri", "triand", "trior", "wand" and "wor" net types
229 - The "config" keyword and library map files
231 - The "disable", "primitive" and "specify" statements
233 - Latched logic (is synthesized as logic with feedback loops)
236 Verilog Attributes and non-standard features
237 ============================================
239 - The 'full_case' attribute on case statements is supported
240 (also the non-standard "// synopsys full_case" directive)
242 - The 'parallel_case' attribute on case statements is supported
243 (also the non-standard "// synopsys parallel_case" directive)
245 - The "// synopsys translate_off" and "// synopsys translate_on"
246 directives are also supported (but the use of `ifdef .. `endif
247 is strongly recommended instead).
249 - The "nomem2reg" attribute on modules or arrays prohibits the
250 automatic early conversion of arrays to separate registers. This
251 is potentially dangerous. Usually the front-end has good reasons
252 for converting an array to a list of registers. Prohibiting this
253 step will likely result in incorrect synthesis results.
255 - The "mem2reg" attribute on modules or arrays forces the early
256 conversion of arrays to separate registers.
258 - The "nomeminit" attribute on modules or arrays prohibits the
259 creation of initialized memories. This effectively puts "mem2reg"
260 on all memories that are written to in an "initial" block and
263 - The "nolatches" attribute on modules or always-blocks
264 prohibits the generation of logic-loops for latches. Instead
265 all not explicitly assigned values default to x-bits. This does
266 not affect clocked storage elements such as flip-flops.
268 - The "nosync" attribute on registers prohibits the generation of a
269 storage element. The register itself will always have all bits set
270 to 'x' (undefined). The variable may only be used as blocking assigned
271 temporary variable within an always block. This is mostly used internally
272 by yosys to synthesize Verilog functions and access arrays.
274 - The "onehot" attribute on wires mark them as onehot state register. This
275 is used for example for memory port sharing and set by the fsm_map pass.
277 - The "blackbox" attribute on modules is used to mark empty stub modules
278 that have the same ports as the real thing but do not contain information
279 on the internal configuration. This modules are only used by the synthesis
280 passes to identify input and output ports of cells. The Verilog backend
281 also does not output blackbox modules on default.
283 - The "keep" attribute on cells and wires is used to mark objects that should
284 never be removed by the optimizer. This is used for example for cells that
285 have hidden connections that are not part of the netlist, such as IO pads.
286 Setting the "keep" attribute on a module has the same effect as setting it
287 on all instances of the module.
289 - The "keep_hierarchy" attribute on cells and modules keeps the "flatten"
290 command from flattening the indicated cells and modules.
292 - The "init" attribute on wires is set by the frontend when a register is
293 initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis
294 to add the necessary reset logic.
296 - The "top" attribute on a module marks this module as the top of the
297 design hierarchy. The "hierarchy" command sets this attribute when called
298 with "-top". Other commands, such as "flatten" and various backends
299 use this attribute to determine the top module.
301 - The "src" attribute is set on cells and wires created by to the string
302 "<hdl-file-name>:<line-number>" by the HDL front-end and is then carried
303 through the synthesis. When entities are combined, a new |-separated
304 string is created that contains all the string from the original entities.
306 - In addition to the (* ... *) attribute syntax, yosys supports
307 the non-standard {* ... *} attribute syntax to set default attributes
308 for everything that comes after the {* ... *} statement. (Reset
309 by adding an empty {* *} statement.)
311 - Modules can be declared with "module mod_name(...);" (with three dots
312 instead of a list of module ports). With this syntax it is sufficient
313 to simply declare a module port as 'input' or 'output' in the module
316 - When defining a macro with `define, all text between triple double quotes
317 is interpreted as macro body, even if it contains unescaped newlines. The
318 tipple double quotes are removed from the macro body. For example:
320 `define MY_MACRO(a, b) """
325 - The attribute "via_celltype" can be used to implement a Verilog task or
326 function by instantiating the specified cell type. The value is the name
327 of the cell type to use. For functions the name of the output port can
328 be specified by appending it to the cell type separated by a whitespace.
329 The body of the task or function is unused in this case and can be used
330 to specify a behavioral model of the cell type for simulation. For example:
332 module my_add3(A, B, C, Y);
334 input [WIDTH-1:0] A, B, C;
335 output [WIDTH-1:0] Y;
341 (* via_celltype = "my_add3 Y" *)
342 (* via_celltype_defparam_WIDTH = 32 *)
343 function [31:0] add3;
344 input [31:0] A, B, C;
352 - A limited subset of DPI-C functions is supported. The plugin mechanism
353 (see "help plugin") can be used load .so files with implementations of
354 DPI-C routines. As a non-standard extension it is possible to specify
355 a plugin alias using the "<alias>:" syntax. for example:
358 import "DPI-C" function foo:round = real my_round (real);
359 parameter real r = my_round(12.345);
362 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
364 - Sized constants (the syntax <size>'s?[bodh]<value>) support constant
365 expressions as <size>. If the expression is not a simple identifier, it
366 must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
368 - The system tasks $finish and $display are supported in initial blocks
369 in and unconditional context (only if/case statements on parameters
370 and constant values). The intended use for this is synthesis-time DRC.
373 Supported features from SystemVerilog
374 =====================================
376 When read_verilog is called with -sv, it accepts some language features
379 - The "assert" statement from SystemVerilog is supported in its most basic
380 form. In module context: "assert property (<expression>);" and within an
381 always block: "assert(<expression>);". It is transformed to a $assert cell.
383 - The keywords "always_comb", "always_ff" and "always_latch", "logic" and
386 Building the documentation
387 ==========================
389 On Ubuntu, texlive needs these packages to be able to build the manual:
391 sudo apt-get install texlive-binaries
392 sudo apt-get install texlive-science # install algorithm2e.sty
393 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
394 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
395 sudo apt-get install texlive-publishers # IEEEtran.cls
397 Also the non-free font luximono should be installed, there is unfortulately
398 no Ubuntu package for this so it should be installed separately using
401 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
402 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
403 getnonfreefonts luximono # installs to /home/user/texmf
405 Then execute, from the root of the repository:
411 - To run `make manual` you need to have installed yosys with `make install`,
412 otherwise it will fail on finding `kernel/yosys.h` while building