3 Aquila is a Wishbone-compatible, 32-bit, LPC slave device with 64-bit DMA support.
5 Aquila provides two interfaces to the system:
6 1. A 32-bit Wishbone slave interface with IRQ support. All functions are supported on this interface in a CPU-interactive mode.
7 2. A 64-bit Wishbone master (DMA) interface, providing high speed data access and configurable DMA access protection ranges.
17 ## [0x00 - 0x07] Device ID
19 Device make/model unique identifier for PnP functionality
20 Fixed value: 0x7c5250545350494d
22 ## [0x08 - 0x0b] Device version
24 Device revision (stepping)
26 | Bits | Description |
27 |-------|---------------|
28 | 31:16 | Major version |
29 | 15:8 | Minor version |
32 ## [0x0c - 0x0f] System clock frequency
34 Can be used to set divisor to meet specific SPI Flash clock frequency requirements
36 ## [0x10 - 0x13] Control register 1
41 - CIRQ: Interrupt request as wired to Wishbone-attached internal CPU
42 - HIRQ: Interrupt request as wired to external host platform over LPC serial IRQ line
44 | Bits | Description |
45 |-------|---------------------------------------------------------------------------------------------------|
47 | 19 | Fire CIRQ on LPC I/O cycle access |
48 | 18 | Fire CIRQ on LPC TPM cycle access |
49 | 17 | Fire CIRQ on LPC firmware cycle access |
50 | 16 | Enable BMC BT interface CIRQ |
51 | 15:8 | IPMI BT I/O port address |
52 | 7 | Use alternate IPMI BT HIRQ (IRQ #11) instead of standard IPMI BT HIRQ (IRQ #10) |
53 | 6 | Enable IPMI BT host interface |
54 | 5 | Enable VUART2 host interface |
55 | 4 | Enable VUART1 host interface |
56 | 3 | Allow LPC I/O cycles from host |
57 | 2 | Allow LPC TPM cycles from host |
58 | 1 | Allow LPC firmware cycles from host |
59 | 0 | Global CIRQ enable, 0 disables all CIRQs, 1 allows any enabled CIRQs to assert main LPC core CIRQ |
61 ## [0x14 - 0x17] Control register 2
65 This register is used only in the CPU-interactive transfer mode. Any activate DMA ranges will take precendence over this register for HOST firmware cycles.
68 - CPU: Wishbone-attached internal CPU
69 - HOST: External host platform attached via LPC
71 | Bits | Description |
72 |-------|----------------------------------------------------------------------------------------------------|
74 | 15:8 | LPC cycle data out (CPU to HOST) |
76 | 1 | Signal LPC bus error to HOST if asserted when bit 0 asserted |
77 | 0 | Assert to transfer data in bits [15:8], [1] to HOST. Completes the active LPC cycle on assertion. |
79 ## [0x18 - 0x1b] LPC address range 1 configuration register 1
83 | Bits | Description |
84 |------|-------------------------------------|
85 | 31 | Enable this LPC slave address range |
86 | 30 | Allow I/O cycles for this range |
87 | 29 | Allow TPM cycles for this range |
89 | 27:0 | LPC range start address |
91 ## [0x1c - 0x1f] LPC address range 1 configuration register 2
95 | Bits | Description |
96 |-------|-----------------------|
98 | 27:0 | LPC range end address |
100 ## [0x20 - 0x23] LPC address range 2 configuration register 1
104 Same bit mapping as "LPC address range 1 configuration register 1"
106 ## [0x24 - 0x27] LPC address range 2 configuration register 2
110 Same bit mapping as "LPC address range 1 configuration register 2"
112 ## [0x28 - 0x2b] LPC address range 3 configuration register 1
116 Same bit mapping as "LPC address range 1 configuration register 1"
118 ## [0x2c - 0x2f] LPC address range 3 configuration register 2
122 Same bit mapping as "LPC address range 1 configuration register 2"
124 ## [0x30 - 0x33] LPC address range 4 configuration register 1
128 Same bit mapping as "LPC address range 1 configuration register 1"
130 ## [0x34 - 0x37] LPC address range 4 configuration register 2
134 Same bit mapping as "LPC address range 1 configuration register 2"
136 ## [0x38 - 0x3b] LPC address range 5 configuration register 1
140 Same bit mapping as "LPC address range 1 configuration register 1"
142 ## [0x3c - 0x3f] LPC address range 5 configuration register 2
146 Same bit mapping as "LPC address range 1 configuration register 2"
148 ## [0x40 - 0x43] LPC address range 6 configuration register 1
152 Same bit mapping as "LPC address range 1 configuration register 1"
154 ## [0x44 - 0x47] LPC address range 6 configuration register 2
158 Same bit mapping as "LPC address range 1 configuration register 2"
160 ## [0x48 - 0x4b] DMA configuration register 1
164 | Bits | Description |
165 |------|---------------------------------------------------------------------------------------------------------------------------|
167 | 7:4 | LPC IDSEL filter |
169 | 2 | IDSEL filter enable. When asserted, the DMA engine will require the LPC IDSEL to match the configured filter IDSEL value |
170 | 1 | Enable DMA for LPC firmware write cycles |
171 | 0 | Enable DMA for LPC firmware read cycles |
173 ## [0x4c - 0x4f] DMA configuration register 2
178 - CPU: Wishbone-attached internal CPU
179 - HOST: External host platform attached via LPC
181 | Bits | Description |
182 |------|------------------------------------|
183 | 31:0 | CPU DMA window base address [31:0] |
185 NOTE: The DMA engine only supports full word length (64 bit) CPU bus alignment, therefore bits [3:0] of this register are hardwired to zero.
187 ## [0x4c - 0x4f] DMA configuration register 3
192 - CPU: Wishbone-attached internal CPU
193 - HOST: External host platform attached via LPC
195 | Bits | Description |
196 |------|-------------------------------------|
197 | 31:0 | CPU DMA window base address [63:32] |
199 ## [0x50 - 0x53] DMA configuration register 4
204 - CPU: Wishbone-attached internal CPU
205 - HOST: External host platform attached via LPC
207 | Bits | Description |
208 |------|------------------------------------|
209 | 31:0 | LPC firmware window length (bytes) |
211 NOTE: The DMA engine only supports full word length (64 bit) CPU bus alignment, therefore bits [3:0] of this register are hardwired to zero.
213 ## [0x54 - 0x57] DMA configuration register 5
218 - CPU: Wishbone-attached internal CPU
219 - HOST: External host platform attached via LPC
221 | Bits | Description |
222 |------|------------------------------------------|
223 | 31:0 | LPC firmware window start offset (bytes) |
225 This register defines the start address (DMA window offset) of the active LPC firmware access window.
227 All LPC firmware transfers start with an implicit LPC base address of 0x0, which corresponds to offset 0x0 in the configured CPU DMA window (see "DMA configuration register 2").
228 This register allows remapping of the LPC base address within the CPU DMA window, thus allowing LPC address 0x0 to be placed anywhere within the configured CPU DMA memory region. In effect, it is the offset into DMA memory space where the LPC memory space origin is placed.
230 Together with the "DMA configuration register 6" register, a defined region of LPC firmware memory space can be set up for DMA access, which is then mapped onto an equivalent region of CPU DMA memory.
232 ## [0x58 - 0x5b] DMA configuration register 6
237 - CPU: Wishbone-attached internal CPU
238 - HOST: External host platform attached via LPC
240 | Bits | Description |
241 |------|----------------------------------------|
242 | 31:0 | LPC firmware window end offset (bytes) |
244 This register defines the end address of the active LPC firmware access window.
246 Together with the "DMA configuration register 5" register, a defined region of LPC firmware memory space can be set up for DMA access, which is then mapped onto an equivalent region of CPU DMA memory.
248 ## [0x5c - 0x5f] DMA configuration register 7
253 - CPU: Wishbone-attached internal CPU
254 - HOST: External host platform attached via LPC
256 | Bits | Description |
257 |------|---------------------------|
258 | 31:0 | LPC firmware address mask |
260 This register defines the mask applied to all inbound LPC firmware space addresses, prior to any mapping of those addresses into the DMA region.
262 This design allows a specific section of CPU DMA memory to be effectively replicated through the entire LPC address space. In particular, it helps to ensure the DMA window data is available at the end of the LPC firmware address space, as expected by various HOST access patterns.
264 ## [0x60 - 0x63] Status register 1
269 - CPU: Wishbone-attached internal CPU
270 - HOST: External host platform attached via LPC
272 | Bits | Description |
273 |-------|------------------------------------------------------------------------------|
275 | 23:20 | IDSEL of pending LPC firmware cycle |
276 | 19:16 | MSIZE of pending LPC firmware cycle |
278 | 4 | Asserted when LPC bus is in external HOST-driven reset |
279 | 3:2 | LPC cycle type from host -- 0 == I/O, 1 == TPM, 2 == firmware, 3 == reserved |
280 | 1 | LPC cycle direction from HOST -- 0 == read, 1 == write |
281 | 0 | Attention flag from LPC core |
283 ## [0x64 - 0x67] Status register 2
288 - CPU: Wishbone-attached internal CPU
289 - HOST: External host platform attached via LPC
291 | Bits | Description |
292 |-------|------------------------------|
294 | 27:0 | Address of pending LPC cycle |
296 This register contains the target LPC address of any pending LPC transaction initiated by the HOST.
298 ## [0x68 - 0x6b] Status register 3
303 - CPU: Wishbone-attached internal CPU
304 - HOST: External host platform attached via LPC
306 | Bits | Description |
307 |------|-----------------------------------------|
309 | 7:0 | HOST-provided data of pending LPC cycle |
311 This register contains the HOST-provided data of any pending LPC transaction initiated by the HOST.
313 The contents of this register are only defined when the LPC cycle type is WRITE; the contents are undefined for all other cycle types.
315 ## [0x6c - 0x6f] Status register 4
320 - CPU: Wishbone-attached internal CPU
321 - HOST: External host platform attached via LPC
322 - CIRQ: Interrupt request as wired to Wishbone-attached internal CPU
323 - HIRQ: Interrupt request as wired to external host platform over LPC serial IRQ line
325 | Bits | Description |
326 |-------|--------------------------------------------------------------------------------------------------|
328 | 11:10 | Reason for VUART2 IRQ assert -- 0 == undefined, 1 == queue threshold reached, 2 == queue timeout |
329 | 9:8 | Reason for VUART1 IRQ assert -- 0 == undefined, 1 == queue threshold reached, 2 == queue timeout |
331 | 6 | LPC I/O cycle CIRQ asserted |
332 | 5 | LPC TPM cycle CIRQ asserted |
333 | 4 | LPC firmware cycle CIRQ asserted |
334 | 3 | IPMI BT CIRQ asserted |
335 | 2 | VUART2 CIRQ asserted |
336 | 1 | VUART1 CIRQ asserted |
337 | 0 | LPC global CIRQ asserted |
341 Aquila is licensed under the terms of the GNU LGPLv3+, with included third party components licensed under Apache 2.0. See LICENSE.aquila for details.
343 # DOCUMENTATION CREDITS
345 (c) 2022 Raptor Engineering, LLC