2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
37 Web Site and Other Resources
38 ============================
40 More information and documentation can be found on the Yosys web site:
41 - https://yosyshq.net/yosys/
43 The "Documentation" page on the web site contains links to more resources,
44 including a manual that even describes some of the Yosys internals:
45 - https://yosyshq.net/yosys/documentation.html
47 The directory `guidelines` contains additional information
48 for people interested in using the Yosys C++ APIs.
50 Users interested in formal verification might want to use the formal verification
51 front-end for Yosys, SymbiYosys:
52 - https://symbiyosys.readthedocs.io/en/latest/
53 - https://github.com/YosysHQ/SymbiYosys
59 Yosys is part of the [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) and the [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build)! The easiest way to use yosys is to install the binary software suite, which contains all required dependencies and related tools.
61 * [Contact YosysHQ](https://www.yosyshq.com/contact) for a [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) Evaluation License and download link
62 * OR go to https://github.com/YosysHQ/oss-cad-suite-build/releases to download the free OSS CAD Suite
63 * Follow the [Install Instructions on GitHub](https://github.com/YosysHQ/oss-cad-suite-build#installation)
65 Make sure to get a Tabby CAD Suite Evaluation License if you need features such as industry-grade SystemVerilog and VHDL parsers!
67 For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet
69 Many Linux distributions also provide Yosys binaries, some more up to date than others. Check with your package manager!
74 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
75 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
76 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
77 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
79 For example on Ubuntu Linux 16.04 LTS the following commands will install all
80 prerequisites for building yosys:
82 $ sudo apt-get install build-essential clang bison flex \
83 libreadline-dev gawk tcl-dev libffi-dev git \
84 graphviz xdot pkg-config python3 libboost-system-dev \
85 libboost-python-dev libboost-filesystem-dev zlib1g-dev
87 Similarily, on Mac OS X Homebrew can be used to install dependencies (from within cloned yosys repository):
89 $ brew tap Homebrew/bundle && brew bundle
93 $ sudo port install bison flex readline gawk libffi \
94 git graphviz pkgconfig python36 boost zlib tcl
96 On FreeBSD use the following command to install all prerequisites:
98 # pkg install bison flex readline gawk libffi\
99 git graphviz pkgconf python3 python36 tcl-wrapper boost-libs
101 On FreeBSD system use gmake instead of make. To run tests use:
102 % MAKE=gmake CC=cc gmake test
104 For Cygwin use the following command to install all prerequisites, or select these additional packages:
106 setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel
108 To configure the build system to use a specific compiler, use one of
113 For other compilers and build configurations it might be
114 necessary to make some changes to the config section of the
117 $ vi Makefile # ..or..
120 To build Yosys simply type 'make' in this directory.
125 Note that this also downloads, builds and installs ABC (using yosys-abc
128 Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:
132 To use a separate (out-of-tree) build directory, provide a path to the Makefile.
134 $ mkdir build; cd build
135 $ make -f ../Makefile
137 Out-of-tree builds require a clean source tree.
142 Yosys can be used with the interactive command shell, with
143 synthesis scripts or with command line arguments. Let's perform
144 a simple synthesis job using the interactive command shell:
149 the command ``help`` can be used to print a list of all available
150 commands and ``help <command>`` to print details on the specified command:
154 reading and elaborating the design using the Verilog frontend:
156 yosys> read -sv tests/simple/fiedler-cooley.v
157 yosys> hierarchy -top up3down5
159 writing the design to the console in Yosys's internal format:
163 convert processes (``always`` blocks) to netlist elements and perform
164 some simple optimizations:
168 display design netlist using ``xdot``:
172 the same thing using ``gv`` as postscript viewer:
174 yosys> show -format ps -viewer gv
176 translating netlist to gate logic and perform some simple optimizations:
180 write design netlist to a new Verilog file:
182 yosys> write_verilog synth.v
184 or using a simple synthesis script:
187 read -sv tests/simple/fiedler-cooley.v
188 hierarchy -top up3down5
189 proc; opt; techmap; opt
190 write_verilog synth.v
194 If ABC is enabled in the Yosys build configuration and a cell library is given
195 in the liberty file ``mycells.lib``, the following synthesis script will
196 synthesize for the given cell library:
199 read -sv tests/simple/fiedler-cooley.v
200 hierarchy -top up3down5
202 # the high-level stuff
203 proc; fsm; opt; memory; opt
205 # mapping to internal cell library
208 # mapping flip-flops to mycells.lib
209 dfflibmap -liberty mycells.lib
211 # mapping logic to mycells.lib
212 abc -liberty mycells.lib
217 If you do not have a liberty file but want to test this synthesis script,
218 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources
221 Liberty file downloads for and information about free and open ASIC standard
222 cell libraries can be found here:
224 - http://www.vlsitechnology.org/html/libraries.html
225 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
227 The command ``synth`` provides a good default synthesis script (see
230 read -sv tests/simple/fiedler-cooley.v
233 # mapping to target cells
234 dfflibmap -liberty mycells.lib
235 abc -liberty mycells.lib
238 The command ``prep`` provides a good default word-level synthesis script, as
239 used in SMT-based formal verification.
242 Unsupported Verilog-2005 Features
243 =================================
245 The following Verilog-2005 features are not supported by
246 Yosys and there are currently no plans to add support
249 - Non-synthesizable language features as defined in
250 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
252 - The ``tri``, ``triand`` and ``trior`` net types
254 - The ``config`` and ``disable`` keywords and library map files
257 Verilog Attributes and non-standard features
258 ============================================
260 - The ``full_case`` attribute on case statements is supported
261 (also the non-standard ``// synopsys full_case`` directive)
263 - The ``parallel_case`` attribute on case statements is supported
264 (also the non-standard ``// synopsys parallel_case`` directive)
266 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
267 directives are also supported (but the use of ``` `ifdef .. `endif ```
268 is strongly recommended instead).
270 - The ``nomem2reg`` attribute on modules or arrays prohibits the
271 automatic early conversion of arrays to separate registers. This
272 is potentially dangerous. Usually the front-end has good reasons
273 for converting an array to a list of registers. Prohibiting this
274 step will likely result in incorrect synthesis results.
276 - The ``mem2reg`` attribute on modules or arrays forces the early
277 conversion of arrays to separate registers.
279 - The ``nomeminit`` attribute on modules or arrays prohibits the
280 creation of initialized memories. This effectively puts ``mem2reg``
281 on all memories that are written to in an ``initial`` block and
284 - The ``nolatches`` attribute on modules or always-blocks
285 prohibits the generation of logic-loops for latches. Instead
286 all not explicitly assigned values default to x-bits. This does
287 not affect clocked storage elements such as flip-flops.
289 - The ``nosync`` attribute on registers prohibits the generation of a
290 storage element. The register itself will always have all bits set
291 to 'x' (undefined). The variable may only be used as blocking assigned
292 temporary variable within an always block. This is mostly used internally
293 by Yosys to synthesize Verilog functions and access arrays.
295 - The ``nowrshmsk`` attribute on a register prohibits the generation of
296 shift-and-mask type circuits for writing to bit slices of that register.
298 - The ``onehot`` attribute on wires mark them as one-hot state register. This
299 is used for example for memory port sharing and set by the fsm_map pass.
301 - The ``blackbox`` attribute on modules is used to mark empty stub modules
302 that have the same ports as the real thing but do not contain information
303 on the internal configuration. This modules are only used by the synthesis
304 passes to identify input and output ports of cells. The Verilog backend
305 also does not output blackbox modules on default. ``read_verilog``, unless
306 called with ``-noblackbox`` will automatically set the blackbox attribute
307 on any empty module it reads.
309 - The ``noblackbox`` attribute set on an empty module prevents ``read_verilog``
310 from automatically setting the blackbox attribute on the module.
312 - The ``whitebox`` attribute on modules triggers the same behavior as
313 ``blackbox``, but is for whitebox modules, i.e. library modules that
314 contain a behavioral model of the cell type.
316 - The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog``
317 is run in `-lib` mode. Otherwise it's automatically removed.
319 - The ``dynports`` attribute is used by the Verilog front-end to mark modules
320 that have ports with a width that depends on a parameter.
322 - The ``hdlname`` attribute is used by some passes to document the original
323 (HDL) name of a module when renaming a module. It should contain a single
324 name, or, when describing a hierarchical name in a flattened design, multiple
325 names separated by a single space character.
327 - The ``keep`` attribute on cells and wires is used to mark objects that should
328 never be removed by the optimizer. This is used for example for cells that
329 have hidden connections that are not part of the netlist, such as IO pads.
330 Setting the ``keep`` attribute on a module has the same effect as setting it
331 on all instances of the module.
333 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
334 command from flattening the indicated cells and modules.
336 - The ``init`` attribute on wires is set by the frontend when a register is
337 initialized "FPGA-style" with ``reg foo = val``. It can be used during
338 synthesis to add the necessary reset logic.
340 - The ``top`` attribute on a module marks this module as the top of the
341 design hierarchy. The ``hierarchy`` command sets this attribute when called
342 with ``-top``. Other commands, such as ``flatten`` and various backends
343 use this attribute to determine the top module.
345 - The ``src`` attribute is set on cells and wires created by to the string
346 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
347 through the synthesis. When entities are combined, a new |-separated
348 string is created that contains all the string from the original entities.
350 - The ``defaultvalue`` attribute is used to store default values for
351 module inputs. The attribute is attached to the input wire by the HDL
352 front-end when the input is declared with a default value.
354 - The ``parameter`` and ``localparam`` attributes are used to mark wires
355 that represent module parameters or localparams (when the HDL front-end
356 is run in ``-pwires`` mode).
358 - Wires marked with the ``hierconn`` attribute are connected to wires with the
359 same name (format ``cell_name.identifier``) when they are imported from
360 sub-modules by ``flatten``.
362 - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
363 module to mark it as a clock buffer output, and thus prevent ``clkbufmap``
364 from inserting another clock buffer on a net driven by such output.
366 - The ``clkbuf_sink`` attribute can be set on an input port of a module to
367 request clock buffer insertion by the ``clkbufmap`` pass.
369 - The ``clkbuf_inv`` attribute can be set on an output port of a module
370 with the value set to the name of an input port of that module. When
371 the ``clkbufmap`` would otherwise insert a clock buffer on this output,
372 it will instead try inserting the clock buffer on the input port (this
373 is used to implement clock inverter cells that clock buffer insertion
376 - The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent
377 automatic clock buffer insertion by ``clkbufmap``. This behaviour can be
378 overridden by providing a custom selection to ``clkbufmap``.
380 - The ``invertible_pin`` attribute can be set on a port to mark it as
381 invertible via a cell parameter. The name of the inversion parameter
382 is specified as the value of this attribute. The value of the inversion
383 parameter must be of the same width as the port, with 1 indicating
384 an inverted bit and 0 indicating a non-inverted bit.
386 - The ``iopad_external_pin`` attribute on a blackbox module's port marks
387 it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
388 from inserting another pad cell on it.
390 - The module attribute ``abc9_lut`` is an integer attribute indicating to
391 `abc9` that this module describes a LUT with an area cost of this value, and
392 propagation delays described using `specify` statements.
394 - The module attribute ``abc9_box`` is a boolean specifying a black/white-box
395 definition, with propagation delays described using `specify` statements, for
398 - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
399 carry-out (if output port) ports of a box. This information is necessary for
400 `abc9` to preserve the integrity of carry-chains. Specifying this attribute
401 onto a bus port will affect only its most significant bit.
403 - The module attribute ``abc9_flop`` is a boolean marking the module as a
404 flip-flop. This allows `abc9` to analyse its contents in order to perform
405 sequential synthesis.
407 - The frontend sets attributes ``always_comb``, ``always_latch`` and
408 ``always_ff`` on processes derived from SystemVerilog style always blocks
409 according to the type of the always. These are checked for correctness in
412 - The cell attribute ``wildcard_port_conns`` represents wildcard port
413 connections (SystemVerilog ``.*``). These are resolved to concrete
414 connections to matching wires in ``hierarchy``.
416 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
417 the non-standard ``{* ... *}`` attribute syntax to set default attributes
418 for everything that comes after the ``{* ... *}`` statement. (Reset
419 by adding an empty ``{* *}`` statement.)
421 - In module parameter and port declarations, and cell port and parameter
422 lists, a trailing comma is ignored. This simplifies writing Verilog code
423 generators a bit in some cases.
425 - Modules can be declared with ``module mod_name(...);`` (with three dots
426 instead of a list of module ports). With this syntax it is sufficient
427 to simply declare a module port as 'input' or 'output' in the module
430 - When defining a macro with `define, all text between triple double quotes
431 is interpreted as macro body, even if it contains unescaped newlines. The
432 triple double quotes are removed from the macro body. For example:
434 `define MY_MACRO(a, b) """
439 - The attribute ``via_celltype`` can be used to implement a Verilog task or
440 function by instantiating the specified cell type. The value is the name
441 of the cell type to use. For functions the name of the output port can
442 be specified by appending it to the cell type separated by a whitespace.
443 The body of the task or function is unused in this case and can be used
444 to specify a behavioral model of the cell type for simulation. For example:
446 module my_add3(A, B, C, Y);
448 input [WIDTH-1:0] A, B, C;
449 output [WIDTH-1:0] Y;
455 (* via_celltype = "my_add3 Y" *)
456 (* via_celltype_defparam_WIDTH = 32 *)
457 function [31:0] add3;
458 input [31:0] A, B, C;
466 - The ``wiretype`` attribute is added by the verilog parser for wires of a
467 typedef'd type to indicate the type identifier.
469 - Various ``enum_value_{value}`` attributes are added to wires of an enumerated type
470 to give a map of possible enum items to their values.
472 - The ``enum_base_type`` attribute is added to enum items to indicate which
473 enum they belong to (enums -- anonymous and otherwise -- are
474 automatically named with an auto-incrementing counter). Note that enums
475 are currently not strongly typed.
477 - A limited subset of DPI-C functions is supported. The plugin mechanism
478 (see ``help plugin``) can be used to load .so files with implementations
479 of DPI-C routines. As a non-standard extension it is possible to specify
480 a plugin alias using the ``<alias>:`` syntax. For example:
483 import "DPI-C" function foo:round = real my_round (real);
484 parameter real r = my_round(12.345);
487 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
489 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
490 expressions as ``<size>``. If the expression is not a simple identifier, it
491 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
493 - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in
494 initial blocks in an unconditional context (only if/case statements on
495 expressions over parameters and constant values are allowed). The intended
496 use for this is synthesis-time DRC.
498 - There is limited support for converting ``specify`` .. ``endspecify``
499 statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells,
500 for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
501 enable this functionality. (By default these blocks are ignored.)
503 - The ``reprocess_after`` internal attribute is used by the Verilog frontend to
504 mark cells with bindings which might depend on the specified instantiated
505 module. Modules with such cells will be reprocessed during the ``hierarchy``
506 pass once the referenced module definition(s) become available.
509 Non-standard or SystemVerilog features for formal verification
510 ==============================================================
512 - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
513 when ``read_verilog`` is called with ``-formal``.
515 - The system task ``$initstate`` evaluates to 1 in the initial state and
518 - The system function ``$anyconst`` evaluates to any constant value. This is
519 equivalent to declaring a reg as ``rand const``, but also works outside
520 of checkers. (Yosys also supports ``rand const`` outside checkers.)
522 - The system function ``$anyseq`` evaluates to any value, possibly a different
523 value in each cycle. This is equivalent to declaring a reg as ``rand``,
524 but also works outside of checkers. (Yosys also supports ``rand``
525 variables outside checkers.)
527 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
528 formal exist-forall problems. Assumptions only hold if the trace satisfies
529 the assumption for all ``$allconst/$allseq`` values. For assertions and cover
530 statements it is sufficient if just one ``$allconst/$allseq`` value triggers
531 the property (similar to ``$anyconst/$anyseq``).
533 - Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute
534 (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
535 by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
537 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
538 supported in any clocked block.
540 - The syntax ``@($global_clock)`` can be used to create FFs that have no
541 explicit clock input (``$ff`` cells). The same can be achieved by using
542 ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
543 is marked with the ``(* gclk *)`` Verilog attribute.
546 Supported features from SystemVerilog
547 =====================================
549 When ``read_verilog`` is called with ``-sv``, it accepts some language features
552 - The ``assert`` statement from SystemVerilog is supported in its most basic
553 form. In module context: ``assert property (<expression>);`` and within an
554 always block: ``assert(<expression>);``. It is transformed to an ``$assert`` cell.
556 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
557 also supported. The same limitations as with the ``assert`` statement apply.
559 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
560 and ``bit`` are supported.
562 - Declaring free variables with ``rand`` and ``rand const`` is supported.
564 - Checkers without a port list that do not need to be instantiated (but instead
565 behave like a named block) are supported.
567 - SystemVerilog packages are supported. Once a SystemVerilog file is read
568 into a design with ``read_verilog``, all its packages are available to
569 SystemVerilog files being read into the same design afterwards.
571 - typedefs are supported (including inside packages)
572 - type casts are currently not supported
574 - enums are supported (including inside packages)
575 - but are currently not strongly typed
577 - packed structs and unions are supported.
579 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
580 ports are inputs or outputs are supported.
583 Building the documentation
584 ==========================
586 Note that there is no need to build the manual if you just want to read it.
587 Simply download the PDF from https://yosyshq.net/yosys/documentation.html
590 On Ubuntu, texlive needs these packages to be able to build the manual:
592 sudo apt-get install texlive-binaries
593 sudo apt-get install texlive-science # install algorithm2e.sty
594 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
595 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
596 sudo apt-get install texlive-publishers # IEEEtran.cls
598 Also the non-free font luximono should be installed, there is unfortunately
599 no Ubuntu package for this so it should be installed separately using
602 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
603 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
604 getnonfreefonts luximono # installs to /home/user/texmf
606 Then execute, from the root of the repository:
612 - To run `make manual` you need to have installed Yosys with `make install`,
613 otherwise it will fail on finding `kernel/yosys.h` while building