3 A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy
6 ## Simulation using ghdl
8 - Build micropython. If you aren't building on a ppc64le box you
9 will need a cross compiler. If it isn't available on your distro
10 grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
13 git clone https://github.com/mikey/micropython
21 - Microwatt uses ghdl for simulation. Either install this from your
22 distro or build it. Next build microwatt:
25 git clone https://github.com/antonblanchard/microwatt
30 - Link in the micropython image:
33 ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
36 - Now run microwatt, sending debug output to /dev/null:
42 ## Synthesis on Xilinx FPGAs using Vivado
44 - Install Vivado (I'm using the free 2019.1 webpack edition).
49 source /opt/Xilinx/Vivado/2019.1/settings64.sh
55 pip3 install --user -U fusesoc
58 - Create a working directory and point FuseSoC at microwatt:
61 mkdir microwatt-fusesoc
63 fusesoc library add microwatt /path/to/microwatt/
66 - Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
69 fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
72 - To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
75 fusesoc run --target=nexys_video microwatt
80 - A simple test suite containing random execution test cases and a couple of
81 micropython test cases can be run with:
89 This is functional, but very simple. We still have quite a lot to do:
91 - Need to implement a simple non pipelined divide
92 - There are a few instructions still to be implemented
93 - Need to add caches and bypassing (in progress)
94 - Need to add supervisor state (in progress)