2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2017 Clifford Wolf <clifford@clifford.at>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
40 More information and documentation can be found on the Yosys web site:
41 http://www.clifford.at/yosys/
46 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
47 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
48 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
49 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
51 For example on Ubuntu Linux 16.04 LTS the following commands will install all
52 prerequisites for building yosys:
54 $ sudo apt-get install build-essential clang bison flex \
55 libreadline-dev gawk tcl-dev libffi-dev git \
56 graphviz xdot pkg-config python3
58 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
60 $ brew tap Homebrew/bundle && brew bundle
61 $ sudo port install bison flex readline gawk libffi \
62 git graphviz pkgconfig python36
64 On FreeBSD use the following command to install all prerequisites:
66 # pkg install bison flex readline gawk libffi\
67 git graphviz pkgconfig python3 python36 tcl-wrapper
69 On FreeBSD system use gmake instead of make. To run tests use:
70 % MAKE=gmake CC=cc gmake test
72 For Cygwin use the following command to install all prerequisites, or select these additional packages:
74 setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel
76 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
77 as a source distribution for Visual Studio. Visit the Yosys download page for
78 more information: http://www.clifford.at/yosys/download.html
80 To configure the build system to use a specific compiler, use one of
85 For other compilers and build configurations it might be
86 necessary to make some changes to the config section of the
89 $ vi Makefile # ..or..
92 To build Yosys simply type 'make' in this directory.
98 Note that this also downloads, builds and installs ABC (using yosys-abc
104 Yosys can be used with the interactive command shell, with
105 synthesis scripts or with command line arguments. Let's perform
106 a simple synthesis job using the interactive command shell:
111 the command ``help`` can be used to print a list of all available
112 commands and ``help <command>`` to print details on the specified command:
116 reading the design using the Verilog frontend:
118 yosys> read_verilog tests/simple/fiedler-cooley.v
120 writing the design to the console in yosys's internal format:
124 elaborate design hierarchy:
128 convert processes (``always`` blocks) to netlist elements and perform
129 some simple optimizations:
133 display design netlist using ``xdot``:
137 the same thing using ``gv`` as postscript viewer:
139 yosys> show -format ps -viewer gv
141 translating netlist to gate logic and perform some simple optimizations:
145 write design netlist to a new Verilog file:
147 yosys> write_verilog synth.v
149 a similar synthesis can be performed using yosys command line options only:
151 $ ./yosys -o synth.v -p hierarchy -p proc -p opt \
152 -p techmap -p opt tests/simple/fiedler-cooley.v
154 or using a simple synthesis script:
157 read_verilog tests/simple/fiedler-cooley.v
158 hierarchy; proc; opt; techmap; opt
159 write_verilog synth.v
163 It is also possible to only have the synthesis commands but not the read/write
164 commands in the synthesis script:
167 hierarchy; proc; opt; techmap; opt
169 $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys
171 The following very basic synthesis script should work well with all designs:
173 # check design hierarchy
176 # translate processes (always blocks)
179 # detect and optimize FSM encodings
182 # implement memories (arrays)
185 # convert to gate logic
188 If ABC is enabled in the Yosys build configuration and a cell library is given
189 in the liberty file ``mycells.lib``, the following synthesis script will
190 synthesize for the given cell library:
192 # the high-level stuff
193 hierarchy; proc; fsm; opt; memory; opt
195 # mapping to internal cell library
198 # mapping flip-flops to mycells.lib
199 dfflibmap -liberty mycells.lib
201 # mapping logic to mycells.lib
202 abc -liberty mycells.lib
207 If you do not have a liberty file but want to test this synthesis script,
208 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources.
210 Liberty file downloads for and information about free and open ASIC standard
211 cell libraries can be found here:
213 - http://www.vlsitechnology.org/html/libraries.html
214 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
216 The command ``synth`` provides a good default synthesis script (see
217 ``help synth``). If possible a synthesis script should borrow from ``synth``.
220 # the high-level stuff
224 # mapping to internal cells
226 dfflibmap -liberty mycells.lib
227 abc -liberty mycells.lib
230 Yosys is under construction. A more detailed documentation will follow.
233 Unsupported Verilog-2005 Features
234 =================================
236 The following Verilog-2005 features are not supported by
237 yosys and there are currently no plans to add support
240 - Non-synthesizable language features as defined in
241 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
243 - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
245 - The ``config`` keyword and library map files
247 - The ``disable``, ``primitive`` and ``specify`` statements
249 - Latched logic (is synthesized as logic with feedback loops)
252 Verilog Attributes and non-standard features
253 ============================================
255 - The ``full_case`` attribute on case statements is supported
256 (also the non-standard ``// synopsys full_case`` directive)
258 - The ``parallel_case`` attribute on case statements is supported
259 (also the non-standard ``// synopsys parallel_case`` directive)
261 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
262 directives are also supported (but the use of ``` `ifdef .. `endif ```
263 is strongly recommended instead).
265 - The ``nomem2reg`` attribute on modules or arrays prohibits the
266 automatic early conversion of arrays to separate registers. This
267 is potentially dangerous. Usually the front-end has good reasons
268 for converting an array to a list of registers. Prohibiting this
269 step will likely result in incorrect synthesis results.
271 - The ``mem2reg`` attribute on modules or arrays forces the early
272 conversion of arrays to separate registers.
274 - The ``nomeminit`` attribute on modules or arrays prohibits the
275 creation of initialized memories. This effectively puts ``mem2reg``
276 on all memories that are written to in an ``initial`` block and
279 - The ``nolatches`` attribute on modules or always-blocks
280 prohibits the generation of logic-loops for latches. Instead
281 all not explicitly assigned values default to x-bits. This does
282 not affect clocked storage elements such as flip-flops.
284 - The ``nosync`` attribute on registers prohibits the generation of a
285 storage element. The register itself will always have all bits set
286 to 'x' (undefined). The variable may only be used as blocking assigned
287 temporary variable within an always block. This is mostly used internally
288 by yosys to synthesize Verilog functions and access arrays.
290 - The ``onehot`` attribute on wires mark them as onehot state register. This
291 is used for example for memory port sharing and set by the fsm_map pass.
293 - The ``blackbox`` attribute on modules is used to mark empty stub modules
294 that have the same ports as the real thing but do not contain information
295 on the internal configuration. This modules are only used by the synthesis
296 passes to identify input and output ports of cells. The Verilog backend
297 also does not output blackbox modules on default.
299 - The ``keep`` attribute on cells and wires is used to mark objects that should
300 never be removed by the optimizer. This is used for example for cells that
301 have hidden connections that are not part of the netlist, such as IO pads.
302 Setting the ``keep`` attribute on a module has the same effect as setting it
303 on all instances of the module.
305 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
306 command from flattening the indicated cells and modules.
308 - The ``init`` attribute on wires is set by the frontend when a register is
309 initialized "FPGA-style" with ``reg foo = val``. It can be used during
310 synthesis to add the necessary reset logic.
312 - The ``top`` attribute on a module marks this module as the top of the
313 design hierarchy. The ``hierarchy`` command sets this attribute when called
314 with ``-top``. Other commands, such as ``flatten`` and various backends
315 use this attribute to determine the top module.
317 - The ``src`` attribute is set on cells and wires created by to the string
318 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
319 through the synthesis. When entities are combined, a new |-separated
320 string is created that contains all the string from the original entities.
322 - In addition to the ``(* ... *)`` attribute syntax, yosys supports
323 the non-standard ``{* ... *}`` attribute syntax to set default attributes
324 for everything that comes after the ``{* ... *}`` statement. (Reset
325 by adding an empty ``{* *}`` statement.)
327 - In module parameter and port declarations, and cell port and parameter
328 lists, a trailing comma is ignored. This simplifies writing verilog code
329 generators a bit in some cases.
331 - Modules can be declared with ``module mod_name(...);`` (with three dots
332 instead of a list of module ports). With this syntax it is sufficient
333 to simply declare a module port as 'input' or 'output' in the module
336 - When defining a macro with `define, all text between triple double quotes
337 is interpreted as macro body, even if it contains unescaped newlines. The
338 tipple double quotes are removed from the macro body. For example:
340 `define MY_MACRO(a, b) """
345 - The attribute ``via_celltype`` can be used to implement a Verilog task or
346 function by instantiating the specified cell type. The value is the name
347 of the cell type to use. For functions the name of the output port can
348 be specified by appending it to the cell type separated by a whitespace.
349 The body of the task or function is unused in this case and can be used
350 to specify a behavioral model of the cell type for simulation. For example:
352 module my_add3(A, B, C, Y);
354 input [WIDTH-1:0] A, B, C;
355 output [WIDTH-1:0] Y;
361 (* via_celltype = "my_add3 Y" *)
362 (* via_celltype_defparam_WIDTH = 32 *)
363 function [31:0] add3;
364 input [31:0] A, B, C;
372 - A limited subset of DPI-C functions is supported. The plugin mechanism
373 (see ``help plugin``) can be used to load .so files with implementations
374 of DPI-C routines. As a non-standard extension it is possible to specify
375 a plugin alias using the ``<alias>:`` syntax. For example:
378 import "DPI-C" function foo:round = real my_round (real);
379 parameter real r = my_round(12.345);
382 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
384 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
385 expressions as <size>. If the expression is not a simple identifier, it
386 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
388 - The system tasks ``$finish`` and ``$display`` are supported in initial blocks
389 in an unconditional context (only if/case statements on parameters
390 and constant values). The intended use for this is synthesis-time DRC.
393 Non-standard or SystemVerilog features for formal verification
394 ==============================================================
396 - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
397 when ``read_verilog`` is called with ``-formal``.
399 - The system task ``$initstate`` evaluates to 1 in the initial state and
402 - The system function ``$anyconst`` evaluates to any constant value. This is
403 equivalent to declaring a reg as ``rand const``, but also works outside
404 of checkers. (Yosys also supports ``rand const`` outside checkers.)
406 - The system function ``$anyseq`` evaluates to any value, possibly a different
407 value in each cycle. This is equivalent to declaring a reg as ``rand``,
408 but also works outside of checkers. (Yosys also supports ``rand``
409 variables outside checkers.)
411 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
412 formal exist-forall problems. Assumptions only hold if the trace satisfies
413 the assumtion for all ``$allconst/$allseq`` values. For assertions and cover
414 statements it is sufficient if just one ``$allconst/$allseq`` value triggers
415 the property (similar to ``$anyconst/$anyseq``).
417 - Wires/registers decalred using the ``anyconst/anyseq/allconst/allseq`` attribute
418 (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
419 by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
421 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
422 supported in any clocked block.
424 - The syntax ``@($global_clock)`` can be used to create FFs that have no
425 explicit clock input ($ff cells). The same can be achieved by using
426 ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
427 is marked with the ``(* gclk *)`` Verilog attribute.
430 Supported features from SystemVerilog
431 =====================================
433 When ``read_verilog`` is called with ``-sv``, it accepts some language features
436 - The ``assert`` statement from SystemVerilog is supported in its most basic
437 form. In module context: ``assert property (<expression>);`` and within an
438 always block: ``assert(<expression>);``. It is transformed to a $assert cell.
440 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
441 also supported. The same limitations as with the ``assert`` statement apply.
443 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
444 and ``bit`` are supported.
446 - Declaring free variables with ``rand`` and ``rand const`` is supported.
448 - Checkers without a port list that do not need to be instantiated (but instead
449 behave like a named block) are supported.
451 - SystemVerilog packages are supported. Once a SystemVerilog file is read
452 into a design with ``read_verilog``, all its packages are available to
453 SystemVerilog files being read into the same design afterwards.
456 Building the documentation
457 ==========================
459 Note that there is no need to build the manual if you just want to read it.
460 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
463 On Ubuntu, texlive needs these packages to be able to build the manual:
465 sudo apt-get install texlive-binaries
466 sudo apt-get install texlive-science # install algorithm2e.sty
467 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
468 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
469 sudo apt-get install texlive-publishers # IEEEtran.cls
471 Also the non-free font luximono should be installed, there is unfortunately
472 no Ubuntu package for this so it should be installed separately using
475 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
476 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
477 getnonfreefonts luximono # installs to /home/user/texmf
479 Then execute, from the root of the repository:
485 - To run `make manual` you need to have installed yosys with `make install`,
486 otherwise it will fail on finding `kernel/yosys.h` while building