2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2016 Clifford Wolf <clifford@clifford.at>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
40 More information and documentation can be found on the Yosys web site:
41 http://www.clifford.at/yosys/
46 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
47 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
48 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
49 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
51 For example on Ubuntu Linux 16.04 LTS the following commands will install all
52 prerequisites for building yosys:
54 $ sudo apt-get install build-essential clang bison flex \
55 libreadline-dev gawk tcl-dev libffi-dev git mercurial \
56 graphviz xdot pkg-config python3
58 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
60 $ brew tap Homebrew/bundle && brew bundle
61 $ sudo port install bison flex readline gawk libffi \
62 git mercurial graphviz pkgconfig python36
64 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
65 as a source distribution for Visual Studio. Visit the Yosys download page for
66 more information: http://www.clifford.at/yosys/download.html
68 To configure the build system to use a specific compiler, use one of
73 For other compilers and build configurations it might be
74 necessary to make some changes to the config section of the
77 $ vi Makefile # ..or..
80 To build Yosys simply type 'make' in this directory.
86 Note that this also downloads, builds and installs ABC (using yosys-abc
92 Yosys can be used with the interactive command shell, with
93 synthesis scripts or with command line arguments. Let's perform
94 a simple synthesis job using the interactive command shell:
99 the command ``help`` can be used to print a list of all available
100 commands and ``help <command>`` to print details on the specified command:
104 reading the design using the Verilog frontend:
106 yosys> read_verilog tests/simple/fiedler-cooley.v
108 writing the design to the console in yosys's internal format:
112 elaborate design hierarchy:
116 convert processes (``always`` blocks) to netlist elements and perform
117 some simple optimizations:
121 display design netlist using ``xdot``:
125 the same thing using ``gv`` as postscript viewer:
127 yosys> show -format ps -viewer gv
129 translating netlist to gate logic and perform some simple optimizations:
133 write design netlist to a new Verilog file:
135 yosys> write_verilog synth.v
137 a similar synthesis can be performed using yosys command line options only:
139 $ ./yosys -o synth.v -p hierarchy -p proc -p opt \
140 -p techmap -p opt tests/simple/fiedler-cooley.v
142 or using a simple synthesis script:
145 read_verilog tests/simple/fiedler-cooley.v
146 hierarchy; proc; opt; techmap; opt
147 write_verilog synth.v
151 It is also possible to only have the synthesis commands but not the read/write
152 commands in the synthesis script:
155 hierarchy; proc; opt; techmap; opt
157 $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys
159 The following very basic synthesis script should work well with all designs:
161 # check design hierarchy
164 # translate processes (always blocks)
167 # detect and optimize FSM encodings
170 # implement memories (arrays)
173 # convert to gate logic
176 If ABC is enabled in the Yosys build configuration and a cell library is given
177 in the liberty file ``mycells.lib``, the following synthesis script will
178 synthesize for the given cell library:
180 # the high-level stuff
181 hierarchy; proc; fsm; opt; memory; opt
183 # mapping to internal cell library
186 # mapping flip-flops to mycells.lib
187 dfflibmap -liberty mycells.lib
189 # mapping logic to mycells.lib
190 abc -liberty mycells.lib
195 If you do not have a liberty file but want to test this synthesis script,
196 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources.
198 Liberty file downloads for and information about free and open ASIC standard
199 cell libraries can be found here:
201 - http://www.vlsitechnology.org/html/libraries.html
202 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
204 The command ``synth`` provides a good default synthesis script (see
205 ``help synth``). If possible a synthesis script should borrow from ``synth``.
208 # the high-level stuff
212 # mapping to internal cells
214 dfflibmap -liberty mycells.lib
215 abc -liberty mycells.lib
218 Yosys is under construction. A more detailed documentation will follow.
221 Unsupported Verilog-2005 Features
222 =================================
224 The following Verilog-2005 features are not supported by
225 yosys and there are currently no plans to add support
228 - Non-synthesizable language features as defined in
229 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
231 - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
233 - The ``config`` keyword and library map files
235 - The ``disable``, ``primitive`` and ``specify`` statements
237 - Latched logic (is synthesized as logic with feedback loops)
240 Verilog Attributes and non-standard features
241 ============================================
243 - The ``full_case`` attribute on case statements is supported
244 (also the non-standard ``// synopsys full_case`` directive)
246 - The ``parallel_case`` attribute on case statements is supported
247 (also the non-standard ``// synopsys parallel_case`` directive)
249 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
250 directives are also supported (but the use of ``` `ifdef .. `endif ```
251 is strongly recommended instead).
253 - The ``nomem2reg`` attribute on modules or arrays prohibits the
254 automatic early conversion of arrays to separate registers. This
255 is potentially dangerous. Usually the front-end has good reasons
256 for converting an array to a list of registers. Prohibiting this
257 step will likely result in incorrect synthesis results.
259 - The ``mem2reg`` attribute on modules or arrays forces the early
260 conversion of arrays to separate registers.
262 - The ``nomeminit`` attribute on modules or arrays prohibits the
263 creation of initialized memories. This effectively puts ``mem2reg``
264 on all memories that are written to in an ``initial`` block and
267 - The ``nolatches`` attribute on modules or always-blocks
268 prohibits the generation of logic-loops for latches. Instead
269 all not explicitly assigned values default to x-bits. This does
270 not affect clocked storage elements such as flip-flops.
272 - The ``nosync`` attribute on registers prohibits the generation of a
273 storage element. The register itself will always have all bits set
274 to 'x' (undefined). The variable may only be used as blocking assigned
275 temporary variable within an always block. This is mostly used internally
276 by yosys to synthesize Verilog functions and access arrays.
278 - The ``onehot`` attribute on wires mark them as onehot state register. This
279 is used for example for memory port sharing and set by the fsm_map pass.
281 - The ``blackbox`` attribute on modules is used to mark empty stub modules
282 that have the same ports as the real thing but do not contain information
283 on the internal configuration. This modules are only used by the synthesis
284 passes to identify input and output ports of cells. The Verilog backend
285 also does not output blackbox modules on default.
287 - The ``keep`` attribute on cells and wires is used to mark objects that should
288 never be removed by the optimizer. This is used for example for cells that
289 have hidden connections that are not part of the netlist, such as IO pads.
290 Setting the ``keep`` attribute on a module has the same effect as setting it
291 on all instances of the module.
293 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
294 command from flattening the indicated cells and modules.
296 - The ``init`` attribute on wires is set by the frontend when a register is
297 initialized "FPGA-style" with ``reg foo = val``. It can be used during
298 synthesis to add the necessary reset logic.
300 - The ``top`` attribute on a module marks this module as the top of the
301 design hierarchy. The ``hierarchy`` command sets this attribute when called
302 with ``-top``. Other commands, such as ``flatten`` and various backends
303 use this attribute to determine the top module.
305 - The ``src`` attribute is set on cells and wires created by to the string
306 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
307 through the synthesis. When entities are combined, a new |-separated
308 string is created that contains all the string from the original entities.
310 - In addition to the ``(* ... *)`` attribute syntax, yosys supports
311 the non-standard ``{* ... *}`` attribute syntax to set default attributes
312 for everything that comes after the ``{* ... *}`` statement. (Reset
313 by adding an empty ``{* *}`` statement.)
315 - In module parameter and port declarations, and cell port and parameter
316 lists, a trailing comma is ignored. This simplifies writing verilog code
317 generators a bit in some cases.
319 - Modules can be declared with ``module mod_name(...);`` (with three dots
320 instead of a list of module ports). With this syntax it is sufficient
321 to simply declare a module port as 'input' or 'output' in the module
324 - When defining a macro with `define, all text between triple double quotes
325 is interpreted as macro body, even if it contains unescaped newlines. The
326 tipple double quotes are removed from the macro body. For example:
328 `define MY_MACRO(a, b) """
333 - The attribute ``via_celltype`` can be used to implement a Verilog task or
334 function by instantiating the specified cell type. The value is the name
335 of the cell type to use. For functions the name of the output port can
336 be specified by appending it to the cell type separated by a whitespace.
337 The body of the task or function is unused in this case and can be used
338 to specify a behavioral model of the cell type for simulation. For example:
340 module my_add3(A, B, C, Y);
342 input [WIDTH-1:0] A, B, C;
343 output [WIDTH-1:0] Y;
349 (* via_celltype = "my_add3 Y" *)
350 (* via_celltype_defparam_WIDTH = 32 *)
351 function [31:0] add3;
352 input [31:0] A, B, C;
360 - A limited subset of DPI-C functions is supported. The plugin mechanism
361 (see ``help plugin``) can be used to load .so files with implementations
362 of DPI-C routines. As a non-standard extension it is possible to specify
363 a plugin alias using the ``<alias>:`` syntax. For example:
366 import "DPI-C" function foo:round = real my_round (real);
367 parameter real r = my_round(12.345);
370 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
372 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
373 expressions as <size>. If the expression is not a simple identifier, it
374 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
376 - The system tasks ``$finish`` and ``$display`` are supported in initial blocks
377 in an unconditional context (only if/case statements on parameters
378 and constant values). The intended use for this is synthesis-time DRC.
381 Non-standard or SystemVerilog features for formal verification
382 ==============================================================
384 - Support for ``assert``, ``assume``, ``restrict``, and ``cover'' is enabled
385 when ``read_verilog`` is called with ``-formal``.
387 - The system task ``$initstate`` evaluates to 1 in the initial state and
390 - The system task ``$anyconst`` evaluates to any constant value. This is
391 equivalent to declaring a reg as ``rand const``, but also works outside
392 of checkers. (Yosys also supports ``rand const`` outside checkers.)
394 - The system task ``$anyseq`` evaluates to any value, possibly a different
395 value in each cycle. This is equivalent to declaring a reg as ``rand``,
396 but also works outside of checkers. (Yosys also supports ``rand``
397 variables outside checkers.)
399 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
400 supported in any clocked block.
402 - The syntax ``@($global_clock)`` can be used to create FFs that have no
403 explicit clock input ($ff cells).
406 Supported features from SystemVerilog
407 =====================================
409 When ``read_verilog`` is called with ``-sv``, it accepts some language features
412 - The ``assert`` statement from SystemVerilog is supported in its most basic
413 form. In module context: ``assert property (<expression>);`` and within an
414 always block: ``assert(<expression>);``. It is transformed to a $assert cell.
416 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
417 also supported. The same limitations as with the ``assert`` statement apply.
419 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
420 and ``bit`` are supported.
422 - Declaring free variables with ``rand`` and ``rand const`` is supported.
424 - Checkers without a port list that do not need to be instantiated (but instead
425 behave like a named block) are supported.
427 - SystemVerilog packages are supported. Once a SystemVerilog file is read
428 into a design with ``read_verilog``, all its packages are available to
429 SystemVerilog files being read into the same design afterwards.
432 Building the documentation
433 ==========================
435 Note that there is no need to build the manual if you just want to read it.
436 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
439 On Ubuntu, texlive needs these packages to be able to build the manual:
441 sudo apt-get install texlive-binaries
442 sudo apt-get install texlive-science # install algorithm2e.sty
443 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
444 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
445 sudo apt-get install texlive-publishers # IEEEtran.cls
447 Also the non-free font luximono should be installed, there is unfortunately
448 no Ubuntu package for this so it should be installed separately using
451 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
452 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
453 getnonfreefonts luximono # installs to /home/user/texmf
455 Then execute, from the root of the repository:
461 - To run `make manual` you need to have installed yosys with `make install`,
462 otherwise it will fail on finding `kernel/yosys.h` while building