2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2019 Clifford Wolf <clifford@clifford.at>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
37 Web Site and Other Resources
38 ============================
40 More information and documentation can be found on the Yosys web site:
41 - http://www.clifford.at/yosys/
43 The "Documentation" page on the web site contains links to more resources,
44 including a manual that even describes some of the Yosys internals:
45 - http://www.clifford.at/yosys/documentation.html
47 The file `CodingReadme` in this directory contains additional information
48 for people interested in using the Yosys C++ APIs.
50 Users interested in formal verification might want to use the formal verification
51 front-end for Yosys, SymbiYosys:
52 - https://symbiyosys.readthedocs.io/en/latest/
53 - https://github.com/YosysHQ/SymbiYosys
59 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
60 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
61 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
62 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
64 For example on Ubuntu Linux 16.04 LTS the following commands will install all
65 prerequisites for building yosys:
67 $ sudo apt-get install build-essential clang bison flex \
68 libreadline-dev gawk tcl-dev libffi-dev git \
69 graphviz xdot pkg-config python3 libboost-system-dev \
70 libboost-python-dev libboost-filesystem-dev zlib1g-dev
72 Similarily, on Mac OS X Homebrew can be used to install dependencies:
74 $ brew tap Homebrew/bundle && brew bundle
78 $ sudo port install bison flex readline gawk libffi \
79 git graphviz pkgconfig python36 boost zlib tcl
81 On FreeBSD use the following command to install all prerequisites:
83 # pkg install bison flex readline gawk libffi\
84 git graphviz pkgconf python3 python36 tcl-wrapper boost-libs
86 On FreeBSD system use gmake instead of make. To run tests use:
87 % MAKE=gmake CC=cc gmake test
89 For Cygwin use the following command to install all prerequisites, or select these additional packages:
91 setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel
93 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
94 as a source distribution for Visual Studio. Visit the Yosys download page for
95 more information: http://www.clifford.at/yosys/download.html
97 To configure the build system to use a specific compiler, use one of
102 For other compilers and build configurations it might be
103 necessary to make some changes to the config section of the
106 $ vi Makefile # ..or..
109 To build Yosys simply type 'make' in this directory.
114 Note that this also downloads, builds and installs ABC (using yosys-abc
117 Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:
124 Yosys can be used with the interactive command shell, with
125 synthesis scripts or with command line arguments. Let's perform
126 a simple synthesis job using the interactive command shell:
131 the command ``help`` can be used to print a list of all available
132 commands and ``help <command>`` to print details on the specified command:
136 reading and elaborating the design using the Verilog frontend:
138 yosys> read -sv tests/simple/fiedler-cooley.v
139 yosys> hierarchy -top up3down5
141 writing the design to the console in Yosys's internal format:
145 convert processes (``always`` blocks) to netlist elements and perform
146 some simple optimizations:
150 display design netlist using ``xdot``:
154 the same thing using ``gv`` as postscript viewer:
156 yosys> show -format ps -viewer gv
158 translating netlist to gate logic and perform some simple optimizations:
162 write design netlist to a new Verilog file:
164 yosys> write_verilog synth.v
166 or using a simple synthesis script:
169 read -sv tests/simple/fiedler-cooley.v
170 hierarchy -top up3down5
171 proc; opt; techmap; opt
172 write_verilog synth.v
176 If ABC is enabled in the Yosys build configuration and a cell library is given
177 in the liberty file ``mycells.lib``, the following synthesis script will
178 synthesize for the given cell library:
181 read -sv tests/simple/fiedler-cooley.v
182 hierarchy -top up3down5
184 # the high-level stuff
185 proc; fsm; opt; memory; opt
187 # mapping to internal cell library
190 # mapping flip-flops to mycells.lib
191 dfflibmap -liberty mycells.lib
193 # mapping logic to mycells.lib
194 abc -liberty mycells.lib
199 If you do not have a liberty file but want to test this synthesis script,
200 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources
203 Liberty file downloads for and information about free and open ASIC standard
204 cell libraries can be found here:
206 - http://www.vlsitechnology.org/html/libraries.html
207 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
209 The command ``synth`` provides a good default synthesis script (see
212 read -sv tests/simple/fiedler-cooley.v
215 # mapping to target cells
216 dfflibmap -liberty mycells.lib
217 abc -liberty mycells.lib
220 The command ``prep`` provides a good default word-level synthesis script, as
221 used in SMT-based formal verification.
224 Unsupported Verilog-2005 Features
225 =================================
227 The following Verilog-2005 features are not supported by
228 Yosys and there are currently no plans to add support
231 - Non-synthesizable language features as defined in
232 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
234 - The ``tri``, ``triand`` and ``trior`` net types
236 - The ``config`` and ``disable`` keywords and library map files
239 Verilog Attributes and non-standard features
240 ============================================
242 - The ``full_case`` attribute on case statements is supported
243 (also the non-standard ``// synopsys full_case`` directive)
245 - The ``parallel_case`` attribute on case statements is supported
246 (also the non-standard ``// synopsys parallel_case`` directive)
248 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
249 directives are also supported (but the use of ``` `ifdef .. `endif ```
250 is strongly recommended instead).
252 - The ``nomem2reg`` attribute on modules or arrays prohibits the
253 automatic early conversion of arrays to separate registers. This
254 is potentially dangerous. Usually the front-end has good reasons
255 for converting an array to a list of registers. Prohibiting this
256 step will likely result in incorrect synthesis results.
258 - The ``mem2reg`` attribute on modules or arrays forces the early
259 conversion of arrays to separate registers.
261 - The ``nomeminit`` attribute on modules or arrays prohibits the
262 creation of initialized memories. This effectively puts ``mem2reg``
263 on all memories that are written to in an ``initial`` block and
266 - The ``nolatches`` attribute on modules or always-blocks
267 prohibits the generation of logic-loops for latches. Instead
268 all not explicitly assigned values default to x-bits. This does
269 not affect clocked storage elements such as flip-flops.
271 - The ``nosync`` attribute on registers prohibits the generation of a
272 storage element. The register itself will always have all bits set
273 to 'x' (undefined). The variable may only be used as blocking assigned
274 temporary variable within an always block. This is mostly used internally
275 by Yosys to synthesize Verilog functions and access arrays.
277 - The ``onehot`` attribute on wires mark them as one-hot state register. This
278 is used for example for memory port sharing and set by the fsm_map pass.
280 - The ``blackbox`` attribute on modules is used to mark empty stub modules
281 that have the same ports as the real thing but do not contain information
282 on the internal configuration. This modules are only used by the synthesis
283 passes to identify input and output ports of cells. The Verilog backend
284 also does not output blackbox modules on default. ``read_verilog``, unless
285 called with ``-noblackbox`` will automatically set the blackbox attribute
286 on any empty module it reads.
288 - The ``noblackbox`` attribute set on an empty module prevents ``read_verilog``
289 from automatically setting the blackbox attribute on the module.
291 - The ``whitebox`` attribute on modules triggers the same behavior as
292 ``blackbox``, but is for whitebox modules, i.e. library modules that
293 contain a behavioral model of the cell type.
295 - The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog``
296 is run in `-lib` mode. Otherwise it's automatically removed.
298 - The ``dynports`` attribute is used by the Verilog front-end to mark modules
299 that have ports with a width that depends on a parameter.
301 - The ``hdlname`` attribute is used by some passes to document the original
302 (HDL) name of a module when renaming a module.
304 - The ``keep`` attribute on cells and wires is used to mark objects that should
305 never be removed by the optimizer. This is used for example for cells that
306 have hidden connections that are not part of the netlist, such as IO pads.
307 Setting the ``keep`` attribute on a module has the same effect as setting it
308 on all instances of the module.
310 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
311 command from flattening the indicated cells and modules.
313 - The ``init`` attribute on wires is set by the frontend when a register is
314 initialized "FPGA-style" with ``reg foo = val``. It can be used during
315 synthesis to add the necessary reset logic.
317 - The ``top`` attribute on a module marks this module as the top of the
318 design hierarchy. The ``hierarchy`` command sets this attribute when called
319 with ``-top``. Other commands, such as ``flatten`` and various backends
320 use this attribute to determine the top module.
322 - The ``src`` attribute is set on cells and wires created by to the string
323 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
324 through the synthesis. When entities are combined, a new |-separated
325 string is created that contains all the string from the original entities.
327 - The ``defaultvalue`` attribute is used to store default values for
328 module inputs. The attribute is attached to the input wire by the HDL
329 front-end when the input is declared with a default value.
331 - The ``parameter`` and ``localparam`` attributes are used to mark wires
332 that represent module parameters or localparams (when the HDL front-end
333 is run in ``-pwires`` mode).
335 - Wires marked with the ``hierconn`` attribute are connected to wires with the
336 same name (format ``cell_name.identifier``) when they are imported from
337 sub-modules by ``flatten``.
339 - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
340 module to mark it as a clock buffer output, and thus prevent ``clkbufmap``
341 from inserting another clock buffer on a net driven by such output.
343 - The ``clkbuf_sink`` attribute can be set on an input port of a module to
344 request clock buffer insertion by the ``clkbufmap`` pass.
346 - The ``clkbuf_inv`` attribute can be set on an output port of a module
347 with the value set to the name of an input port of that module. When
348 the ``clkbufmap`` would otherwise insert a clock buffer on this output,
349 it will instead try inserting the clock buffer on the input port (this
350 is used to implement clock inverter cells that clock buffer insertion
353 - The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent
354 automatic clock buffer insertion by ``clkbufmap``. This behaviour can be
355 overridden by providing a custom selection to ``clkbufmap``.
357 - The ``invertible_pin`` attribute can be set on a port to mark it as
358 invertible via a cell parameter. The name of the inversion parameter
359 is specified as the value of this attribute. The value of the inversion
360 parameter must be of the same width as the port, with 1 indicating
361 an inverted bit and 0 indicating a non-inverted bit.
363 - The ``iopad_external_pin`` attribute on a blackbox module's port marks
364 it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
365 from inserting another pad cell on it.
367 - The module attribute ``abc9_box_id`` specifies a positive integer linking a
368 blackbox or whitebox definition to a corresponding entry in a `abc9`
371 - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
372 carry-out (if output port) ports of a box. This information is necessary for
373 `abc9` to preserve the integrity of carry-chains. Specifying this attribute
374 onto a bus port will affect only its most significant bit.
376 - The port attribute ``abc9_arrival`` specifies an integer (for output ports
377 only) to be used as the arrival time of this sequential port. It can be used,
378 for example, to specify the clk-to-Q delay of a flip-flop for consideration
379 during `abc9` techmapping.
381 - The module attribute ``abc9_flop`` is a boolean marking the module as a
382 flip-flop. This allows `abc9` to analyse its contents in order to perform
383 sequential synthesis.
385 - The frontend sets attributes ``always_comb``, ``always_latch`` and
386 ``always_ff`` on processes derived from SystemVerilog style always blocks
387 according to the type of the always. These are checked for correctness in
390 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
391 the non-standard ``{* ... *}`` attribute syntax to set default attributes
392 for everything that comes after the ``{* ... *}`` statement. (Reset
393 by adding an empty ``{* *}`` statement.)
395 - In module parameter and port declarations, and cell port and parameter
396 lists, a trailing comma is ignored. This simplifies writing Verilog code
397 generators a bit in some cases.
399 - Modules can be declared with ``module mod_name(...);`` (with three dots
400 instead of a list of module ports). With this syntax it is sufficient
401 to simply declare a module port as 'input' or 'output' in the module
404 - When defining a macro with `define, all text between triple double quotes
405 is interpreted as macro body, even if it contains unescaped newlines. The
406 triple double quotes are removed from the macro body. For example:
408 `define MY_MACRO(a, b) """
413 - The attribute ``via_celltype`` can be used to implement a Verilog task or
414 function by instantiating the specified cell type. The value is the name
415 of the cell type to use. For functions the name of the output port can
416 be specified by appending it to the cell type separated by a whitespace.
417 The body of the task or function is unused in this case and can be used
418 to specify a behavioral model of the cell type for simulation. For example:
420 module my_add3(A, B, C, Y);
422 input [WIDTH-1:0] A, B, C;
423 output [WIDTH-1:0] Y;
429 (* via_celltype = "my_add3 Y" *)
430 (* via_celltype_defparam_WIDTH = 32 *)
431 function [31:0] add3;
432 input [31:0] A, B, C;
440 - A limited subset of DPI-C functions is supported. The plugin mechanism
441 (see ``help plugin``) can be used to load .so files with implementations
442 of DPI-C routines. As a non-standard extension it is possible to specify
443 a plugin alias using the ``<alias>:`` syntax. For example:
446 import "DPI-C" function foo:round = real my_round (real);
447 parameter real r = my_round(12.345);
450 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
452 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
453 expressions as ``<size>``. If the expression is not a simple identifier, it
454 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
456 - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in
457 initial blocks in an unconditional context (only if/case statements on
458 expressions over parameters and constant values are allowed). The intended
459 use for this is synthesis-time DRC.
461 - There is limited support for converting ``specify`` .. ``endspecify``
462 statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells,
463 for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
464 enable this functionality. (By default these blocks are ignored.)
467 Non-standard or SystemVerilog features for formal verification
468 ==============================================================
470 - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
471 when ``read_verilog`` is called with ``-formal``.
473 - The system task ``$initstate`` evaluates to 1 in the initial state and
476 - The system function ``$anyconst`` evaluates to any constant value. This is
477 equivalent to declaring a reg as ``rand const``, but also works outside
478 of checkers. (Yosys also supports ``rand const`` outside checkers.)
480 - The system function ``$anyseq`` evaluates to any value, possibly a different
481 value in each cycle. This is equivalent to declaring a reg as ``rand``,
482 but also works outside of checkers. (Yosys also supports ``rand``
483 variables outside checkers.)
485 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
486 formal exist-forall problems. Assumptions only hold if the trace satisfies
487 the assumption for all ``$allconst/$allseq`` values. For assertions and cover
488 statements it is sufficient if just one ``$allconst/$allseq`` value triggers
489 the property (similar to ``$anyconst/$anyseq``).
491 - Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute
492 (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
493 by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
495 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
496 supported in any clocked block.
498 - The syntax ``@($global_clock)`` can be used to create FFs that have no
499 explicit clock input (``$ff`` cells). The same can be achieved by using
500 ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
501 is marked with the ``(* gclk *)`` Verilog attribute.
504 Supported features from SystemVerilog
505 =====================================
507 When ``read_verilog`` is called with ``-sv``, it accepts some language features
510 - The ``assert`` statement from SystemVerilog is supported in its most basic
511 form. In module context: ``assert property (<expression>);`` and within an
512 always block: ``assert(<expression>);``. It is transformed to an ``$assert`` cell.
514 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
515 also supported. The same limitations as with the ``assert`` statement apply.
517 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
518 and ``bit`` are supported.
520 - Declaring free variables with ``rand`` and ``rand const`` is supported.
522 - Checkers without a port list that do not need to be instantiated (but instead
523 behave like a named block) are supported.
525 - SystemVerilog packages are supported. Once a SystemVerilog file is read
526 into a design with ``read_verilog``, all its packages are available to
527 SystemVerilog files being read into the same design afterwards.
529 - typedefs are supported (including inside packages)
531 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
532 ports are inputs or outputs are supported.
535 Building the documentation
536 ==========================
538 Note that there is no need to build the manual if you just want to read it.
539 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
542 On Ubuntu, texlive needs these packages to be able to build the manual:
544 sudo apt-get install texlive-binaries
545 sudo apt-get install texlive-science # install algorithm2e.sty
546 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
547 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
548 sudo apt-get install texlive-publishers # IEEEtran.cls
550 Also the non-free font luximono should be installed, there is unfortunately
551 no Ubuntu package for this so it should be installed separately using
554 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
555 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
556 getnonfreefonts luximono # installs to /home/user/texmf
558 Then execute, from the root of the repository:
564 - To run `make manual` you need to have installed Yosys with `make install`,
565 otherwise it will fail on finding `kernel/yosys.h` while building