2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2016 Clifford Wolf <clifford@clifford.at>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
40 More information and documentation can be found on the Yosys web site:
41 http://www.clifford.at/yosys/
46 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
47 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
48 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
49 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
51 For example on Ubuntu Linux 16.04 LTS the following commands will install all
52 prerequisites for building yosys:
54 $ sudo apt-get install build-essential clang bison flex \
55 libreadline-dev gawk tcl-dev libffi-dev git mercurial \
56 graphviz xdot pkg-config python3
58 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
60 $ brew install bison flex gawk libffi \
61 git mercurial graphviz pkg-config python3
62 $ sudo port install bison flex readline gawk libffi \
63 git mercurial graphviz pkgconfig python36
65 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
66 as a source distribution for Visual Studio. Visit the Yosys download page for
67 more information: http://www.clifford.at/yosys/download.html
69 To configure the build system to use a specific compiler, use one of
74 For other compilers and build configurations it might be
75 necessary to make some changes to the config section of the
78 $ vi Makefile # ..or..
81 To build Yosys simply type 'make' in this directory.
87 Note that this also downloads, builds and installs ABC (using yosys-abc
93 Yosys can be used with the interactive command shell, with
94 synthesis scripts or with command line arguments. Let's perform
95 a simple synthesis job using the interactive command shell:
100 the command ``help`` can be used to print a list of all available
101 commands and ``help <command>`` to print details on the specified command:
105 reading the design using the Verilog frontend:
107 yosys> read_verilog tests/simple/fiedler-cooley.v
109 writing the design to the console in yosys's internal format:
113 elaborate design hierarchy:
117 convert processes (``always`` blocks) to netlist elements and perform
118 some simple optimizations:
122 display design netlist using ``xdot``:
126 the same thing using ``gv`` as postscript viewer:
128 yosys> show -format ps -viewer gv
130 translating netlist to gate logic and perform some simple optimizations:
134 write design netlist to a new Verilog file:
136 yosys> write_verilog synth.v
138 a similar synthesis can be performed using yosys command line options only:
140 $ ./yosys -o synth.v -p hierarchy -p proc -p opt \
141 -p techmap -p opt tests/simple/fiedler-cooley.v
143 or using a simple synthesis script:
146 read_verilog tests/simple/fiedler-cooley.v
147 hierarchy; proc; opt; techmap; opt
148 write_verilog synth.v
152 It is also possible to only have the synthesis commands but not the read/write
153 commands in the synthesis script:
156 hierarchy; proc; opt; techmap; opt
158 $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys
160 The following very basic synthesis script should work well with all designs:
162 # check design hierarchy
165 # translate processes (always blocks)
168 # detect and optimize FSM encodings
171 # implement memories (arrays)
174 # convert to gate logic
177 If ABC is enabled in the Yosys build configuration and a cell library is given
178 in the liberty file ``mycells.lib``, the following synthesis script will
179 synthesize for the given cell library:
181 # the high-level stuff
182 hierarchy; proc; fsm; opt; memory; opt
184 # mapping to internal cell library
187 # mapping flip-flops to mycells.lib
188 dfflibmap -liberty mycells.lib
190 # mapping logic to mycells.lib
191 abc -liberty mycells.lib
196 If you do not have a liberty file but want to test this synthesis script,
197 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources.
199 Liberty file downloads for and information about free and open ASIC standard
200 cell libraries can be found here:
202 - http://www.vlsitechnology.org/html/libraries.html
203 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
205 The command ``synth`` provides a good default synthesis script (see
206 ``help synth``). If possible a synthesis script should borrow from ``synth``.
209 # the high-level stuff
213 # mapping to internal cells
215 dfflibmap -liberty mycells.lib
216 abc -liberty mycells.lib
219 Yosys is under construction. A more detailed documentation will follow.
222 Unsupported Verilog-2005 Features
223 =================================
225 The following Verilog-2005 features are not supported by
226 yosys and there are currently no plans to add support
229 - Non-synthesizable language features as defined in
230 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
232 - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
234 - The ``config`` keyword and library map files
236 - The ``disable``, ``primitive`` and ``specify`` statements
238 - Latched logic (is synthesized as logic with feedback loops)
241 Verilog Attributes and non-standard features
242 ============================================
244 - The ``full_case`` attribute on case statements is supported
245 (also the non-standard ``// synopsys full_case`` directive)
247 - The ``parallel_case`` attribute on case statements is supported
248 (also the non-standard ``// synopsys parallel_case`` directive)
250 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
251 directives are also supported (but the use of ``` `ifdef .. `endif ```
252 is strongly recommended instead).
254 - The ``nomem2reg`` attribute on modules or arrays prohibits the
255 automatic early conversion of arrays to separate registers. This
256 is potentially dangerous. Usually the front-end has good reasons
257 for converting an array to a list of registers. Prohibiting this
258 step will likely result in incorrect synthesis results.
260 - The ``mem2reg`` attribute on modules or arrays forces the early
261 conversion of arrays to separate registers.
263 - The ``nomeminit`` attribute on modules or arrays prohibits the
264 creation of initialized memories. This effectively puts ``mem2reg``
265 on all memories that are written to in an ``initial`` block and
268 - The ``nolatches`` attribute on modules or always-blocks
269 prohibits the generation of logic-loops for latches. Instead
270 all not explicitly assigned values default to x-bits. This does
271 not affect clocked storage elements such as flip-flops.
273 - The ``nosync`` attribute on registers prohibits the generation of a
274 storage element. The register itself will always have all bits set
275 to 'x' (undefined). The variable may only be used as blocking assigned
276 temporary variable within an always block. This is mostly used internally
277 by yosys to synthesize Verilog functions and access arrays.
279 - The ``onehot`` attribute on wires mark them as onehot state register. This
280 is used for example for memory port sharing and set by the fsm_map pass.
282 - The ``blackbox`` attribute on modules is used to mark empty stub modules
283 that have the same ports as the real thing but do not contain information
284 on the internal configuration. This modules are only used by the synthesis
285 passes to identify input and output ports of cells. The Verilog backend
286 also does not output blackbox modules on default.
288 - The ``keep`` attribute on cells and wires is used to mark objects that should
289 never be removed by the optimizer. This is used for example for cells that
290 have hidden connections that are not part of the netlist, such as IO pads.
291 Setting the ``keep`` attribute on a module has the same effect as setting it
292 on all instances of the module.
294 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
295 command from flattening the indicated cells and modules.
297 - The ``init`` attribute on wires is set by the frontend when a register is
298 initialized "FPGA-style" with ``reg foo = val``. It can be used during
299 synthesis to add the necessary reset logic.
301 - The ``top`` attribute on a module marks this module as the top of the
302 design hierarchy. The ``hierarchy`` command sets this attribute when called
303 with ``-top``. Other commands, such as ``flatten`` and various backends
304 use this attribute to determine the top module.
306 - The ``src`` attribute is set on cells and wires created by to the string
307 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
308 through the synthesis. When entities are combined, a new |-separated
309 string is created that contains all the string from the original entities.
311 - In addition to the ``(* ... *)`` attribute syntax, yosys supports
312 the non-standard ``{* ... *}`` attribute syntax to set default attributes
313 for everything that comes after the ``{* ... *}`` statement. (Reset
314 by adding an empty ``{* *}`` statement.)
316 - In module parameter and port declarations, and cell port and parameter
317 lists, a trailing comma is ignored. This simplifies writing verilog code
318 generators a bit in some cases.
320 - Modules can be declared with ``module mod_name(...);`` (with three dots
321 instead of a list of module ports). With this syntax it is sufficient
322 to simply declare a module port as 'input' or 'output' in the module
325 - When defining a macro with `define, all text between triple double quotes
326 is interpreted as macro body, even if it contains unescaped newlines. The
327 tipple double quotes are removed from the macro body. For example:
329 `define MY_MACRO(a, b) """
334 - The attribute ``via_celltype`` can be used to implement a Verilog task or
335 function by instantiating the specified cell type. The value is the name
336 of the cell type to use. For functions the name of the output port can
337 be specified by appending it to the cell type separated by a whitespace.
338 The body of the task or function is unused in this case and can be used
339 to specify a behavioral model of the cell type for simulation. For example:
341 module my_add3(A, B, C, Y);
343 input [WIDTH-1:0] A, B, C;
344 output [WIDTH-1:0] Y;
350 (* via_celltype = "my_add3 Y" *)
351 (* via_celltype_defparam_WIDTH = 32 *)
352 function [31:0] add3;
353 input [31:0] A, B, C;
361 - A limited subset of DPI-C functions is supported. The plugin mechanism
362 (see ``help plugin``) can be used to load .so files with implementations
363 of DPI-C routines. As a non-standard extension it is possible to specify
364 a plugin alias using the ``<alias>:`` syntax. For example:
367 import "DPI-C" function foo:round = real my_round (real);
368 parameter real r = my_round(12.345);
371 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
373 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
374 expressions as <size>. If the expression is not a simple identifier, it
375 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
377 - The system tasks ``$finish`` and ``$display`` are supported in initial blocks
378 in an unconditional context (only if/case statements on parameters
379 and constant values). The intended use for this is synthesis-time DRC.
382 Non-standard or SystemVerilog features for formal verification
383 ==============================================================
385 - Support for ``assert``, ``assume``, ``restrict``, and ``cover'' is enabled
386 when ``read_verilog`` is called with ``-formal``.
388 - The system task ``$initstate`` evaluates to 1 in the initial state and
391 - The system task ``$anyconst`` evaluates to any constant value. This is
392 equivalent to declaring a reg as ``rand const``, but also works outside
393 of checkers. (Yosys also supports ``rand const`` outside checkers.)
395 - The system task ``$anyseq`` evaluates to any value, possibly a different
396 value in each cycle. This is equivalent to declaring a reg as ``rand``,
397 but also works outside of checkers. (Yosys also supports ``rand``
398 variables outside checkers.)
400 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
401 supported in any clocked block.
403 - The syntax ``@($global_clock)`` can be used to create FFs that have no
404 explicit clock input ($ff cells).
407 Supported features from SystemVerilog
408 =====================================
410 When ``read_verilog`` is called with ``-sv``, it accepts some language features
413 - The ``assert`` statement from SystemVerilog is supported in its most basic
414 form. In module context: ``assert property (<expression>);`` and within an
415 always block: ``assert(<expression>);``. It is transformed to a $assert cell.
417 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
418 also supported. The same limitations as with the ``assert`` statement apply.
420 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
421 and ``bit`` are supported.
423 - Declaring free variables with ``rand`` and ``rand const`` is supported.
425 - Checkers without a port list that do not need to be instantiated (but instead
426 behave like a named block) are supported.
428 - SystemVerilog packages are supported. Once a SystemVerilog file is read
429 into a design with ``read_verilog``, all its packages are available to
430 SystemVerilog files being read into the same design afterwards.
433 Building the documentation
434 ==========================
436 Note that there is no need to build the manual if you just want to read it.
437 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
440 On Ubuntu, texlive needs these packages to be able to build the manual:
442 sudo apt-get install texlive-binaries
443 sudo apt-get install texlive-science # install algorithm2e.sty
444 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
445 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
446 sudo apt-get install texlive-publishers # IEEEtran.cls
448 Also the non-free font luximono should be installed, there is unfortunately
449 no Ubuntu package for this so it should be installed separately using
452 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
453 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
454 getnonfreefonts luximono # installs to /home/user/texmf
456 Then execute, from the root of the repository:
462 - To run `make manual` you need to have installed yosys with `make install`,
463 otherwise it will fail on finding `kernel/yosys.h` while building