2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2016 Clifford Wolf <clifford@clifford.at>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
40 More information and documentation can be found on the Yosys web site:
41 http://www.clifford.at/yosys/
47 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
48 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
49 TCL, readline and libffi are optional (see ENABLE_* settings in Makefile).
50 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
51 For example on Ubuntu Linux 16.04 LTS the following commands will install all
52 prerequisites for building yosys:
54 $ sudo apt-get install build-essential clang bison flex \
55 libreadline-dev gawk tcl-dev libffi-dev git mercurial \
56 graphviz xdot pkg-config python3
58 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
59 as a source distribution for Visual Studio. Visit the Yosys download page for
60 more information: http://www.clifford.at/yosys/download.html
62 To configure the build system to use a specific compiler, use one of
67 For other compilers and build configurations it might be
68 necessary to make some changes to the config section of the
71 $ vi Makefile # ..or..
74 To build Yosys simply type 'make' in this directory.
80 Note that this also downloads, builds and installs ABC (using yosys-abc
83 Yosys can be used with the interactive command shell, with
84 synthesis scripts or with command line arguments. Let's perform
85 a simple synthesis job using the interactive command shell:
90 the command ``help`` can be used to print a list of all available
91 commands and ``help <command>`` to print details on the specified command:
95 reading the design using the Verilog frontend:
97 yosys> read_verilog tests/simple/fiedler-cooley.v
99 writing the design to the console in yosys's internal format:
103 elaborate design hierarchy:
107 convert processes (``always`` blocks) to netlist elements and perform
108 some simple optimizations:
112 display design netlist using ``xdot``:
116 the same thing using ``gv`` as postscript viewer:
118 yosys> show -format ps -viewer gv
120 translating netlist to gate logic and perform some simple optimizations:
124 write design netlist to a new Verilog file:
126 yosys> write_verilog synth.v
128 a similar synthesis can be performed using yosys command line options only:
130 $ ./yosys -o synth.v -p hierarchy -p proc -p opt \
131 -p techmap -p opt tests/simple/fiedler-cooley.v
133 or using a simple synthesis script:
136 read_verilog tests/simple/fiedler-cooley.v
137 hierarchy; proc; opt; techmap; opt
138 write_verilog synth.v
142 It is also possible to only have the synthesis commands but not the read/write
143 commands in the synthesis script:
146 hierarchy; proc; opt; techmap; opt
148 $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys
150 The following very basic synthesis script should work well with all designs:
152 # check design hierarchy
155 # translate processes (always blocks)
158 # detect and optimize FSM encodings
161 # implement memories (arrays)
164 # convert to gate logic
167 If ABC is enabled in the Yosys build configuration and a cell library is given
168 in the liberty file ``mycells.lib``, the following synthesis script will
169 synthesize for the given cell library:
171 # the high-level stuff
172 hierarchy; proc; fsm; opt; memory; opt
174 # mapping to internal cell library
177 # mapping flip-flops to mycells.lib
178 dfflibmap -liberty mycells.lib
180 # mapping logic to mycells.lib
181 abc -liberty mycells.lib
186 If you do not have a liberty file but want to test this synthesis script,
187 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources.
189 Liberty file downloads for and information about free and open ASIC standard
190 cell libraries can be found here:
192 - http://www.vlsitechnology.org/html/libraries.html
193 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
195 The command ``synth`` provides a good default synthesis script (see
196 ``help synth``). If possible a synthesis script should borrow from ``synth``.
199 # the high-level stuff
203 # mapping to internal cells
205 dfflibmap -liberty mycells.lib
206 abc -liberty mycells.lib
209 Yosys is under construction. A more detailed documentation will follow.
212 Unsupported Verilog-2005 Features
213 =================================
215 The following Verilog-2005 features are not supported by
216 yosys and there are currently no plans to add support
219 - Non-synthesizable language features as defined in
220 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
222 - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
224 - The ``config`` keyword and library map files
226 - The ``disable``, ``primitive`` and ``specify`` statements
228 - Latched logic (is synthesized as logic with feedback loops)
231 Verilog Attributes and non-standard features
232 ============================================
234 - The ``full_case`` attribute on case statements is supported
235 (also the non-standard ``// synopsys full_case`` directive)
237 - The ``parallel_case`` attribute on case statements is supported
238 (also the non-standard ``// synopsys parallel_case`` directive)
240 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
241 directives are also supported (but the use of ``` `ifdef .. `endif ```
242 is strongly recommended instead).
244 - The ``nomem2reg`` attribute on modules or arrays prohibits the
245 automatic early conversion of arrays to separate registers. This
246 is potentially dangerous. Usually the front-end has good reasons
247 for converting an array to a list of registers. Prohibiting this
248 step will likely result in incorrect synthesis results.
250 - The ``mem2reg`` attribute on modules or arrays forces the early
251 conversion of arrays to separate registers.
253 - The ``nomeminit`` attribute on modules or arrays prohibits the
254 creation of initialized memories. This effectively puts ``mem2reg``
255 on all memories that are written to in an ``initial`` block and
258 - The ``nolatches`` attribute on modules or always-blocks
259 prohibits the generation of logic-loops for latches. Instead
260 all not explicitly assigned values default to x-bits. This does
261 not affect clocked storage elements such as flip-flops.
263 - The ``nosync`` attribute on registers prohibits the generation of a
264 storage element. The register itself will always have all bits set
265 to 'x' (undefined). The variable may only be used as blocking assigned
266 temporary variable within an always block. This is mostly used internally
267 by yosys to synthesize Verilog functions and access arrays.
269 - The ``onehot`` attribute on wires mark them as onehot state register. This
270 is used for example for memory port sharing and set by the fsm_map pass.
272 - The ``blackbox`` attribute on modules is used to mark empty stub modules
273 that have the same ports as the real thing but do not contain information
274 on the internal configuration. This modules are only used by the synthesis
275 passes to identify input and output ports of cells. The Verilog backend
276 also does not output blackbox modules on default.
278 - The ``keep`` attribute on cells and wires is used to mark objects that should
279 never be removed by the optimizer. This is used for example for cells that
280 have hidden connections that are not part of the netlist, such as IO pads.
281 Setting the ``keep`` attribute on a module has the same effect as setting it
282 on all instances of the module.
284 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
285 command from flattening the indicated cells and modules.
287 - The ``init`` attribute on wires is set by the frontend when a register is
288 initialized "FPGA-style" with ``reg foo = val``. It can be used during
289 synthesis to add the necessary reset logic.
291 - The ``top`` attribute on a module marks this module as the top of the
292 design hierarchy. The ``hierarchy`` command sets this attribute when called
293 with ``-top``. Other commands, such as ``flatten`` and various backends
294 use this attribute to determine the top module.
296 - The ``src`` attribute is set on cells and wires created by to the string
297 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
298 through the synthesis. When entities are combined, a new |-separated
299 string is created that contains all the string from the original entities.
301 - In addition to the ``(* ... *)`` attribute syntax, yosys supports
302 the non-standard ``{* ... *}`` attribute syntax to set default attributes
303 for everything that comes after the ``{* ... *}`` statement. (Reset
304 by adding an empty ``{* *}`` statement.)
306 - In module parameter and port declarations, and cell port and parameter
307 lists, a trailing comma is ignored. This simplifies writing verilog code
308 generators a bit in some cases.
310 - Modules can be declared with ``module mod_name(...);`` (with three dots
311 instead of a list of module ports). With this syntax it is sufficient
312 to simply declare a module port as 'input' or 'output' in the module
315 - When defining a macro with `define, all text between triple double quotes
316 is interpreted as macro body, even if it contains unescaped newlines. The
317 tipple double quotes are removed from the macro body. For example:
319 `define MY_MACRO(a, b) """
324 - The attribute ``via_celltype`` can be used to implement a Verilog task or
325 function by instantiating the specified cell type. The value is the name
326 of the cell type to use. For functions the name of the output port can
327 be specified by appending it to the cell type separated by a whitespace.
328 The body of the task or function is unused in this case and can be used
329 to specify a behavioral model of the cell type for simulation. For example:
331 module my_add3(A, B, C, Y);
333 input [WIDTH-1:0] A, B, C;
334 output [WIDTH-1:0] Y;
340 (* via_celltype = "my_add3 Y" *)
341 (* via_celltype_defparam_WIDTH = 32 *)
342 function [31:0] add3;
343 input [31:0] A, B, C;
351 - A limited subset of DPI-C functions is supported. The plugin mechanism
352 (see ``help plugin``) can be used to load .so files with implementations
353 of DPI-C routines. As a non-standard extension it is possible to specify
354 a plugin alias using the ``<alias>:`` syntax. For example:
357 import "DPI-C" function foo:round = real my_round (real);
358 parameter real r = my_round(12.345);
361 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
363 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
364 expressions as <size>. If the expression is not a simple identifier, it
365 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
367 - The system tasks ``$finish`` and ``$display`` are supported in initial blocks
368 in an unconditional context (only if/case statements on parameters
369 and constant values). The intended use for this is synthesis-time DRC.
372 Non-standard or SystemVerilog features for formal verification
373 ==============================================================
375 - Support for ``assert``, ``assume``, and ``restrict`` is enabled when
376 ``read_verilog`` is called with ``-formal``.
378 - The system task ``$initstate`` evaluates to 1 in the initial state and
381 - The system task ``$anyconst`` evaluates to any constant value.
383 - The system task ``$anyseq`` evaluates to any value, possibly a different
386 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
387 supported in any clocked block.
389 - The syntax ``@($global_clock)`` can be used to create FFs that have no
390 explicit clock input ($ff cells).
393 Supported features from SystemVerilog
394 =====================================
396 When ``read_verilog`` is called with ``-sv``, it accepts some language features
399 - The ``assert`` statement from SystemVerilog is supported in its most basic
400 form. In module context: ``assert property (<expression>);`` and within an
401 always block: ``assert(<expression>);``. It is transformed to a $assert cell.
403 - The ``assume`` and ``restrict`` statements from SystemVerilog are also
404 supported. The same limitations as with the ``assert`` statement apply.
406 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
407 and ``bit`` are supported.
409 - SystemVerilog packages are supported. Once a SystemVerilog file is read
410 into a design with ``read_verilog``, all its packages are available to
411 SystemVerilog files being read into the same design afterwards.
414 Building the documentation
415 ==========================
417 Note that there is no need to build the manual if you just want to read it.
418 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
421 On Ubuntu, texlive needs these packages to be able to build the manual:
423 sudo apt-get install texlive-binaries
424 sudo apt-get install texlive-science # install algorithm2e.sty
425 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
426 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
427 sudo apt-get install texlive-publishers # IEEEtran.cls
429 Also the non-free font luximono should be installed, there is unfortunately
430 no Ubuntu package for this so it should be installed separately using
433 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
434 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
435 getnonfreefonts luximono # installs to /home/user/texmf
437 Then execute, from the root of the repository:
443 - To run `make manual` you need to have installed yosys with `make install`,
444 otherwise it will fail on finding `kernel/yosys.h` while building