2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
37 Web Site and Other Resources
38 ============================
40 More information and documentation can be found on the Yosys web site:
41 - http://www.clifford.at/yosys/
43 The "Documentation" page on the web site contains links to more resources,
44 including a manual that even describes some of the Yosys internals:
45 - http://www.clifford.at/yosys/documentation.html
47 The file `CodingReadme` in this directory contains additional information
48 for people interested in using the Yosys C++ APIs.
50 Users interested in formal verification might want to use the formal verification
51 front-end for Yosys, SymbiYosys:
52 - https://symbiyosys.readthedocs.io/en/latest/
53 - https://github.com/YosysHQ/SymbiYosys
59 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
60 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
61 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
62 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
64 For example on Ubuntu Linux 16.04 LTS the following commands will install all
65 prerequisites for building yosys:
67 $ sudo apt-get install build-essential clang bison flex \
68 libreadline-dev gawk tcl-dev libffi-dev git \
69 graphviz xdot pkg-config python3 libboost-system-dev \
70 libboost-python-dev libboost-filesystem-dev zlib1g-dev
72 Similarily, on Mac OS X Homebrew can be used to install dependencies (from within cloned yosys repository):
74 $ brew tap Homebrew/bundle && brew bundle
78 $ sudo port install bison flex readline gawk libffi \
79 git graphviz pkgconfig python36 boost zlib tcl
81 On FreeBSD use the following command to install all prerequisites:
83 # pkg install bison flex readline gawk libffi\
84 git graphviz pkgconf python3 python36 tcl-wrapper boost-libs
86 On FreeBSD system use gmake instead of make. To run tests use:
87 % MAKE=gmake CC=cc gmake test
89 For Cygwin use the following command to install all prerequisites, or select these additional packages:
91 setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel
93 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
94 as a source distribution for Visual Studio. Visit the Yosys download page for
95 more information: http://www.clifford.at/yosys/download.html
97 To configure the build system to use a specific compiler, use one of
102 For other compilers and build configurations it might be
103 necessary to make some changes to the config section of the
106 $ vi Makefile # ..or..
109 To build Yosys simply type 'make' in this directory.
114 Note that this also downloads, builds and installs ABC (using yosys-abc
117 Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:
121 To use a separate (out-of-tree) build directory, provide a path to the Makefile.
123 $ mkdir build; cd build
124 $ make -f ../Makefile
126 Out-of-tree builds require a clean source tree.
131 Yosys can be used with the interactive command shell, with
132 synthesis scripts or with command line arguments. Let's perform
133 a simple synthesis job using the interactive command shell:
138 the command ``help`` can be used to print a list of all available
139 commands and ``help <command>`` to print details on the specified command:
143 reading and elaborating the design using the Verilog frontend:
145 yosys> read -sv tests/simple/fiedler-cooley.v
146 yosys> hierarchy -top up3down5
148 writing the design to the console in Yosys's internal format:
152 convert processes (``always`` blocks) to netlist elements and perform
153 some simple optimizations:
157 display design netlist using ``xdot``:
161 the same thing using ``gv`` as postscript viewer:
163 yosys> show -format ps -viewer gv
165 translating netlist to gate logic and perform some simple optimizations:
169 write design netlist to a new Verilog file:
171 yosys> write_verilog synth.v
173 or using a simple synthesis script:
176 read -sv tests/simple/fiedler-cooley.v
177 hierarchy -top up3down5
178 proc; opt; techmap; opt
179 write_verilog synth.v
183 If ABC is enabled in the Yosys build configuration and a cell library is given
184 in the liberty file ``mycells.lib``, the following synthesis script will
185 synthesize for the given cell library:
188 read -sv tests/simple/fiedler-cooley.v
189 hierarchy -top up3down5
191 # the high-level stuff
192 proc; fsm; opt; memory; opt
194 # mapping to internal cell library
197 # mapping flip-flops to mycells.lib
198 dfflibmap -liberty mycells.lib
200 # mapping logic to mycells.lib
201 abc -liberty mycells.lib
206 If you do not have a liberty file but want to test this synthesis script,
207 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources
210 Liberty file downloads for and information about free and open ASIC standard
211 cell libraries can be found here:
213 - http://www.vlsitechnology.org/html/libraries.html
214 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
216 The command ``synth`` provides a good default synthesis script (see
219 read -sv tests/simple/fiedler-cooley.v
222 # mapping to target cells
223 dfflibmap -liberty mycells.lib
224 abc -liberty mycells.lib
227 The command ``prep`` provides a good default word-level synthesis script, as
228 used in SMT-based formal verification.
231 Unsupported Verilog-2005 Features
232 =================================
234 The following Verilog-2005 features are not supported by
235 Yosys and there are currently no plans to add support
238 - Non-synthesizable language features as defined in
239 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
241 - The ``tri``, ``triand`` and ``trior`` net types
243 - The ``config`` and ``disable`` keywords and library map files
246 Verilog Attributes and non-standard features
247 ============================================
249 - The ``full_case`` attribute on case statements is supported
250 (also the non-standard ``// synopsys full_case`` directive)
252 - The ``parallel_case`` attribute on case statements is supported
253 (also the non-standard ``// synopsys parallel_case`` directive)
255 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
256 directives are also supported (but the use of ``` `ifdef .. `endif ```
257 is strongly recommended instead).
259 - The ``nomem2reg`` attribute on modules or arrays prohibits the
260 automatic early conversion of arrays to separate registers. This
261 is potentially dangerous. Usually the front-end has good reasons
262 for converting an array to a list of registers. Prohibiting this
263 step will likely result in incorrect synthesis results.
265 - The ``mem2reg`` attribute on modules or arrays forces the early
266 conversion of arrays to separate registers.
268 - The ``nomeminit`` attribute on modules or arrays prohibits the
269 creation of initialized memories. This effectively puts ``mem2reg``
270 on all memories that are written to in an ``initial`` block and
273 - The ``nolatches`` attribute on modules or always-blocks
274 prohibits the generation of logic-loops for latches. Instead
275 all not explicitly assigned values default to x-bits. This does
276 not affect clocked storage elements such as flip-flops.
278 - The ``nosync`` attribute on registers prohibits the generation of a
279 storage element. The register itself will always have all bits set
280 to 'x' (undefined). The variable may only be used as blocking assigned
281 temporary variable within an always block. This is mostly used internally
282 by Yosys to synthesize Verilog functions and access arrays.
284 - The ``nowrshmsk`` attribute on a register prohibits the generation of
285 shift-and-mask type circuits for writing to bit slices of that register.
287 - The ``onehot`` attribute on wires mark them as one-hot state register. This
288 is used for example for memory port sharing and set by the fsm_map pass.
290 - The ``blackbox`` attribute on modules is used to mark empty stub modules
291 that have the same ports as the real thing but do not contain information
292 on the internal configuration. This modules are only used by the synthesis
293 passes to identify input and output ports of cells. The Verilog backend
294 also does not output blackbox modules on default. ``read_verilog``, unless
295 called with ``-noblackbox`` will automatically set the blackbox attribute
296 on any empty module it reads.
298 - The ``noblackbox`` attribute set on an empty module prevents ``read_verilog``
299 from automatically setting the blackbox attribute on the module.
301 - The ``whitebox`` attribute on modules triggers the same behavior as
302 ``blackbox``, but is for whitebox modules, i.e. library modules that
303 contain a behavioral model of the cell type.
305 - The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog``
306 is run in `-lib` mode. Otherwise it's automatically removed.
308 - The ``dynports`` attribute is used by the Verilog front-end to mark modules
309 that have ports with a width that depends on a parameter.
311 - The ``hdlname`` attribute is used by some passes to document the original
312 (HDL) name of a module when renaming a module.
314 - The ``keep`` attribute on cells and wires is used to mark objects that should
315 never be removed by the optimizer. This is used for example for cells that
316 have hidden connections that are not part of the netlist, such as IO pads.
317 Setting the ``keep`` attribute on a module has the same effect as setting it
318 on all instances of the module.
320 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
321 command from flattening the indicated cells and modules.
323 - The ``init`` attribute on wires is set by the frontend when a register is
324 initialized "FPGA-style" with ``reg foo = val``. It can be used during
325 synthesis to add the necessary reset logic.
327 - The ``top`` attribute on a module marks this module as the top of the
328 design hierarchy. The ``hierarchy`` command sets this attribute when called
329 with ``-top``. Other commands, such as ``flatten`` and various backends
330 use this attribute to determine the top module.
332 - The ``src`` attribute is set on cells and wires created by to the string
333 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
334 through the synthesis. When entities are combined, a new |-separated
335 string is created that contains all the string from the original entities.
337 - The ``defaultvalue`` attribute is used to store default values for
338 module inputs. The attribute is attached to the input wire by the HDL
339 front-end when the input is declared with a default value.
341 - The ``parameter`` and ``localparam`` attributes are used to mark wires
342 that represent module parameters or localparams (when the HDL front-end
343 is run in ``-pwires`` mode).
345 - Wires marked with the ``hierconn`` attribute are connected to wires with the
346 same name (format ``cell_name.identifier``) when they are imported from
347 sub-modules by ``flatten``.
349 - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
350 module to mark it as a clock buffer output, and thus prevent ``clkbufmap``
351 from inserting another clock buffer on a net driven by such output.
353 - The ``clkbuf_sink`` attribute can be set on an input port of a module to
354 request clock buffer insertion by the ``clkbufmap`` pass.
356 - The ``clkbuf_inv`` attribute can be set on an output port of a module
357 with the value set to the name of an input port of that module. When
358 the ``clkbufmap`` would otherwise insert a clock buffer on this output,
359 it will instead try inserting the clock buffer on the input port (this
360 is used to implement clock inverter cells that clock buffer insertion
363 - The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent
364 automatic clock buffer insertion by ``clkbufmap``. This behaviour can be
365 overridden by providing a custom selection to ``clkbufmap``.
367 - The ``invertible_pin`` attribute can be set on a port to mark it as
368 invertible via a cell parameter. The name of the inversion parameter
369 is specified as the value of this attribute. The value of the inversion
370 parameter must be of the same width as the port, with 1 indicating
371 an inverted bit and 0 indicating a non-inverted bit.
373 - The ``iopad_external_pin`` attribute on a blackbox module's port marks
374 it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
375 from inserting another pad cell on it.
377 - The module attribute ``abc9_lut`` is an integer attribute indicating to
378 `abc9` that this module describes a LUT with an area cost of this value, and
379 propagation delays described using `specify` statements.
381 - The module attribute ``abc9_box`` is a boolean specifying a black/white-box
382 definition, with propagation delays described using `specify` statements, for
385 - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
386 carry-out (if output port) ports of a box. This information is necessary for
387 `abc9` to preserve the integrity of carry-chains. Specifying this attribute
388 onto a bus port will affect only its most significant bit.
390 - The module attribute ``abc9_flop`` is a boolean marking the module as a
391 flip-flop. This allows `abc9` to analyse its contents in order to perform
392 sequential synthesis.
394 - The frontend sets attributes ``always_comb``, ``always_latch`` and
395 ``always_ff`` on processes derived from SystemVerilog style always blocks
396 according to the type of the always. These are checked for correctness in
399 - The cell attribute ``wildcard_port_conns`` represents wildcard port
400 connections (SystemVerilog ``.*``). These are resolved to concrete
401 connections to matching wires in ``hierarchy``.
403 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
404 the non-standard ``{* ... *}`` attribute syntax to set default attributes
405 for everything that comes after the ``{* ... *}`` statement. (Reset
406 by adding an empty ``{* *}`` statement.)
408 - In module parameter and port declarations, and cell port and parameter
409 lists, a trailing comma is ignored. This simplifies writing Verilog code
410 generators a bit in some cases.
412 - Modules can be declared with ``module mod_name(...);`` (with three dots
413 instead of a list of module ports). With this syntax it is sufficient
414 to simply declare a module port as 'input' or 'output' in the module
417 - When defining a macro with `define, all text between triple double quotes
418 is interpreted as macro body, even if it contains unescaped newlines. The
419 triple double quotes are removed from the macro body. For example:
421 `define MY_MACRO(a, b) """
426 - The attribute ``via_celltype`` can be used to implement a Verilog task or
427 function by instantiating the specified cell type. The value is the name
428 of the cell type to use. For functions the name of the output port can
429 be specified by appending it to the cell type separated by a whitespace.
430 The body of the task or function is unused in this case and can be used
431 to specify a behavioral model of the cell type for simulation. For example:
433 module my_add3(A, B, C, Y);
435 input [WIDTH-1:0] A, B, C;
436 output [WIDTH-1:0] Y;
442 (* via_celltype = "my_add3 Y" *)
443 (* via_celltype_defparam_WIDTH = 32 *)
444 function [31:0] add3;
445 input [31:0] A, B, C;
453 - The ``wiretype`` attribute is added by the verilog parser for wires of a
454 typedef'd type to indicate the type identifier.
456 - Various ``enum_value_{value}`` attributes are added to wires of an enumerated type
457 to give a map of possible enum items to their values.
459 - The ``enum_base_type`` attribute is added to enum items to indicate which
460 enum they belong to (enums -- anonymous and otherwise -- are
461 automatically named with an auto-incrementing counter). Note that enums
462 are currently not strongly typed.
464 - A limited subset of DPI-C functions is supported. The plugin mechanism
465 (see ``help plugin``) can be used to load .so files with implementations
466 of DPI-C routines. As a non-standard extension it is possible to specify
467 a plugin alias using the ``<alias>:`` syntax. For example:
470 import "DPI-C" function foo:round = real my_round (real);
471 parameter real r = my_round(12.345);
474 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
476 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
477 expressions as ``<size>``. If the expression is not a simple identifier, it
478 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
480 - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in
481 initial blocks in an unconditional context (only if/case statements on
482 expressions over parameters and constant values are allowed). The intended
483 use for this is synthesis-time DRC.
485 - There is limited support for converting ``specify`` .. ``endspecify``
486 statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells,
487 for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
488 enable this functionality. (By default these blocks are ignored.)
491 Non-standard or SystemVerilog features for formal verification
492 ==============================================================
494 - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
495 when ``read_verilog`` is called with ``-formal``.
497 - The system task ``$initstate`` evaluates to 1 in the initial state and
500 - The system function ``$anyconst`` evaluates to any constant value. This is
501 equivalent to declaring a reg as ``rand const``, but also works outside
502 of checkers. (Yosys also supports ``rand const`` outside checkers.)
504 - The system function ``$anyseq`` evaluates to any value, possibly a different
505 value in each cycle. This is equivalent to declaring a reg as ``rand``,
506 but also works outside of checkers. (Yosys also supports ``rand``
507 variables outside checkers.)
509 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
510 formal exist-forall problems. Assumptions only hold if the trace satisfies
511 the assumption for all ``$allconst/$allseq`` values. For assertions and cover
512 statements it is sufficient if just one ``$allconst/$allseq`` value triggers
513 the property (similar to ``$anyconst/$anyseq``).
515 - Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute
516 (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
517 by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
519 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
520 supported in any clocked block.
522 - The syntax ``@($global_clock)`` can be used to create FFs that have no
523 explicit clock input (``$ff`` cells). The same can be achieved by using
524 ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
525 is marked with the ``(* gclk *)`` Verilog attribute.
528 Supported features from SystemVerilog
529 =====================================
531 When ``read_verilog`` is called with ``-sv``, it accepts some language features
534 - The ``assert`` statement from SystemVerilog is supported in its most basic
535 form. In module context: ``assert property (<expression>);`` and within an
536 always block: ``assert(<expression>);``. It is transformed to an ``$assert`` cell.
538 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
539 also supported. The same limitations as with the ``assert`` statement apply.
541 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
542 and ``bit`` are supported.
544 - Declaring free variables with ``rand`` and ``rand const`` is supported.
546 - Checkers without a port list that do not need to be instantiated (but instead
547 behave like a named block) are supported.
549 - SystemVerilog packages are supported. Once a SystemVerilog file is read
550 into a design with ``read_verilog``, all its packages are available to
551 SystemVerilog files being read into the same design afterwards.
553 - typedefs are supported (including inside packages)
554 - type casts are currently not supported
556 - enums are supported (including inside packages)
557 - but are currently not strongly typed
559 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
560 ports are inputs or outputs are supported.
563 Building the documentation
564 ==========================
566 Note that there is no need to build the manual if you just want to read it.
567 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
570 On Ubuntu, texlive needs these packages to be able to build the manual:
572 sudo apt-get install texlive-binaries
573 sudo apt-get install texlive-science # install algorithm2e.sty
574 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
575 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
576 sudo apt-get install texlive-publishers # IEEEtran.cls
578 Also the non-free font luximono should be installed, there is unfortunately
579 no Ubuntu package for this so it should be installed separately using
582 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
583 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
584 getnonfreefonts luximono # installs to /home/user/texmf
586 Then execute, from the root of the repository:
592 - To run `make manual` you need to have installed Yosys with `make install`,
593 otherwise it will fail on finding `kernel/yosys.h` while building