2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
37 Web Site and Other Resources
38 ============================
40 More information and documentation can be found on the Yosys web site:
41 - http://www.clifford.at/yosys/
43 The "Documentation" page on the web site contains links to more resources,
44 including a manual that even describes some of the Yosys internals:
45 - http://www.clifford.at/yosys/documentation.html
47 The file `CodingReadme` in this directory contains additional information
48 for people interested in using the Yosys C++ APIs.
50 Users interested in formal verification might want to use the formal verification
51 front-end for Yosys, SymbiYosys:
52 - https://symbiyosys.readthedocs.io/en/latest/
53 - https://github.com/YosysHQ/SymbiYosys
59 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
60 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
61 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
62 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
64 For example on Ubuntu Linux 16.04 LTS the following commands will install all
65 prerequisites for building yosys:
67 $ sudo apt-get install build-essential clang bison flex \
68 libreadline-dev gawk tcl-dev libffi-dev git \
69 graphviz xdot pkg-config python3
71 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
73 $ brew tap Homebrew/bundle && brew bundle
74 $ sudo port install bison flex readline gawk libffi \
75 git graphviz pkgconfig python36
77 On FreeBSD use the following command to install all prerequisites:
79 # pkg install bison flex readline gawk libffi\
80 git graphviz pkgconfig python3 python36 tcl-wrapper
82 On FreeBSD system use gmake instead of make. To run tests use:
83 % MAKE=gmake CC=cc gmake test
85 For Cygwin use the following command to install all prerequisites, or select these additional packages:
87 setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel
89 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
90 as a source distribution for Visual Studio. Visit the Yosys download page for
91 more information: http://www.clifford.at/yosys/download.html
93 To configure the build system to use a specific compiler, use one of
98 For other compilers and build configurations it might be
99 necessary to make some changes to the config section of the
102 $ vi Makefile # ..or..
105 To build Yosys simply type 'make' in this directory.
111 Note that this also downloads, builds and installs ABC (using yosys-abc
117 Yosys can be used with the interactive command shell, with
118 synthesis scripts or with command line arguments. Let's perform
119 a simple synthesis job using the interactive command shell:
124 the command ``help`` can be used to print a list of all available
125 commands and ``help <command>`` to print details on the specified command:
129 reading the design using the Verilog frontend:
131 yosys> read_verilog tests/simple/fiedler-cooley.v
133 writing the design to the console in Yosys's internal format:
137 elaborate design hierarchy:
141 convert processes (``always`` blocks) to netlist elements and perform
142 some simple optimizations:
146 display design netlist using ``xdot``:
150 the same thing using ``gv`` as postscript viewer:
152 yosys> show -format ps -viewer gv
154 translating netlist to gate logic and perform some simple optimizations:
158 write design netlist to a new Verilog file:
160 yosys> write_verilog synth.v
162 a similar synthesis can be performed using yosys command line options only:
164 $ ./yosys -o synth.v -p hierarchy -p proc -p opt \
165 -p techmap -p opt tests/simple/fiedler-cooley.v
167 or using a simple synthesis script:
170 read_verilog tests/simple/fiedler-cooley.v
171 hierarchy; proc; opt; techmap; opt
172 write_verilog synth.v
176 It is also possible to only have the synthesis commands but not the read/write
177 commands in the synthesis script:
180 hierarchy; proc; opt; techmap; opt
182 $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys
184 The following very basic synthesis script should work well with all designs:
186 # check design hierarchy
189 # translate processes (always blocks)
192 # detect and optimize FSM encodings
195 # implement memories (arrays)
198 # convert to gate logic
201 If ABC is enabled in the Yosys build configuration and a cell library is given
202 in the liberty file ``mycells.lib``, the following synthesis script will
203 synthesize for the given cell library:
205 # the high-level stuff
206 hierarchy; proc; fsm; opt; memory; opt
208 # mapping to internal cell library
211 # mapping flip-flops to mycells.lib
212 dfflibmap -liberty mycells.lib
214 # mapping logic to mycells.lib
215 abc -liberty mycells.lib
220 If you do not have a liberty file but want to test this synthesis script,
221 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources.
223 Liberty file downloads for and information about free and open ASIC standard
224 cell libraries can be found here:
226 - http://www.vlsitechnology.org/html/libraries.html
227 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
229 The command ``synth`` provides a good default synthesis script (see
230 ``help synth``). If possible a synthesis script should borrow from ``synth``.
233 # the high-level stuff
237 # mapping to internal cells
239 dfflibmap -liberty mycells.lib
240 abc -liberty mycells.lib
243 Yosys is under construction. A more detailed documentation will follow.
246 Unsupported Verilog-2005 Features
247 =================================
249 The following Verilog-2005 features are not supported by
250 Yosys and there are currently no plans to add support
253 - Non-synthesizable language features as defined in
254 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
256 - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
258 - The ``config`` keyword and library map files
260 - The ``disable``, ``primitive`` and ``specify`` statements
262 - Latched logic (is synthesized as logic with feedback loops)
265 Verilog Attributes and non-standard features
266 ============================================
268 - The ``full_case`` attribute on case statements is supported
269 (also the non-standard ``// synopsys full_case`` directive)
271 - The ``parallel_case`` attribute on case statements is supported
272 (also the non-standard ``// synopsys parallel_case`` directive)
274 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
275 directives are also supported (but the use of ``` `ifdef .. `endif ```
276 is strongly recommended instead).
278 - The ``nomem2reg`` attribute on modules or arrays prohibits the
279 automatic early conversion of arrays to separate registers. This
280 is potentially dangerous. Usually the front-end has good reasons
281 for converting an array to a list of registers. Prohibiting this
282 step will likely result in incorrect synthesis results.
284 - The ``mem2reg`` attribute on modules or arrays forces the early
285 conversion of arrays to separate registers.
287 - The ``nomeminit`` attribute on modules or arrays prohibits the
288 creation of initialized memories. This effectively puts ``mem2reg``
289 on all memories that are written to in an ``initial`` block and
292 - The ``nolatches`` attribute on modules or always-blocks
293 prohibits the generation of logic-loops for latches. Instead
294 all not explicitly assigned values default to x-bits. This does
295 not affect clocked storage elements such as flip-flops.
297 - The ``nosync`` attribute on registers prohibits the generation of a
298 storage element. The register itself will always have all bits set
299 to 'x' (undefined). The variable may only be used as blocking assigned
300 temporary variable within an always block. This is mostly used internally
301 by Yosys to synthesize Verilog functions and access arrays.
303 - The ``onehot`` attribute on wires mark them as one-hot state register. This
304 is used for example for memory port sharing and set by the fsm_map pass.
306 - The ``blackbox`` attribute on modules is used to mark empty stub modules
307 that have the same ports as the real thing but do not contain information
308 on the internal configuration. This modules are only used by the synthesis
309 passes to identify input and output ports of cells. The Verilog backend
310 also does not output blackbox modules on default.
312 - The ``keep`` attribute on cells and wires is used to mark objects that should
313 never be removed by the optimizer. This is used for example for cells that
314 have hidden connections that are not part of the netlist, such as IO pads.
315 Setting the ``keep`` attribute on a module has the same effect as setting it
316 on all instances of the module.
318 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
319 command from flattening the indicated cells and modules.
321 - The ``init`` attribute on wires is set by the frontend when a register is
322 initialized "FPGA-style" with ``reg foo = val``. It can be used during
323 synthesis to add the necessary reset logic.
325 - The ``top`` attribute on a module marks this module as the top of the
326 design hierarchy. The ``hierarchy`` command sets this attribute when called
327 with ``-top``. Other commands, such as ``flatten`` and various backends
328 use this attribute to determine the top module.
330 - The ``src`` attribute is set on cells and wires created by to the string
331 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
332 through the synthesis. When entities are combined, a new |-separated
333 string is created that contains all the string from the original entities.
335 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
336 the non-standard ``{* ... *}`` attribute syntax to set default attributes
337 for everything that comes after the ``{* ... *}`` statement. (Reset
338 by adding an empty ``{* *}`` statement.)
340 - In module parameter and port declarations, and cell port and parameter
341 lists, a trailing comma is ignored. This simplifies writing Verilog code
342 generators a bit in some cases.
344 - Modules can be declared with ``module mod_name(...);`` (with three dots
345 instead of a list of module ports). With this syntax it is sufficient
346 to simply declare a module port as 'input' or 'output' in the module
349 - When defining a macro with `define, all text between triple double quotes
350 is interpreted as macro body, even if it contains unescaped newlines. The
351 tipple double quotes are removed from the macro body. For example:
353 `define MY_MACRO(a, b) """
358 - The attribute ``via_celltype`` can be used to implement a Verilog task or
359 function by instantiating the specified cell type. The value is the name
360 of the cell type to use. For functions the name of the output port can
361 be specified by appending it to the cell type separated by a whitespace.
362 The body of the task or function is unused in this case and can be used
363 to specify a behavioral model of the cell type for simulation. For example:
365 module my_add3(A, B, C, Y);
367 input [WIDTH-1:0] A, B, C;
368 output [WIDTH-1:0] Y;
374 (* via_celltype = "my_add3 Y" *)
375 (* via_celltype_defparam_WIDTH = 32 *)
376 function [31:0] add3;
377 input [31:0] A, B, C;
385 - A limited subset of DPI-C functions is supported. The plugin mechanism
386 (see ``help plugin``) can be used to load .so files with implementations
387 of DPI-C routines. As a non-standard extension it is possible to specify
388 a plugin alias using the ``<alias>:`` syntax. For example:
391 import "DPI-C" function foo:round = real my_round (real);
392 parameter real r = my_round(12.345);
395 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
397 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
398 expressions as <size>. If the expression is not a simple identifier, it
399 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
401 - The system tasks ``$finish`` and ``$display`` are supported in initial blocks
402 in an unconditional context (only if/case statements on parameters
403 and constant values). The intended use for this is synthesis-time DRC.
406 Non-standard or SystemVerilog features for formal verification
407 ==============================================================
409 - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
410 when ``read_verilog`` is called with ``-formal``.
412 - The system task ``$initstate`` evaluates to 1 in the initial state and
415 - The system function ``$anyconst`` evaluates to any constant value. This is
416 equivalent to declaring a reg as ``rand const``, but also works outside
417 of checkers. (Yosys also supports ``rand const`` outside checkers.)
419 - The system function ``$anyseq`` evaluates to any value, possibly a different
420 value in each cycle. This is equivalent to declaring a reg as ``rand``,
421 but also works outside of checkers. (Yosys also supports ``rand``
422 variables outside checkers.)
424 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
425 formal exist-forall problems. Assumptions only hold if the trace satisfies
426 the assumption for all ``$allconst/$allseq`` values. For assertions and cover
427 statements it is sufficient if just one ``$allconst/$allseq`` value triggers
428 the property (similar to ``$anyconst/$anyseq``).
430 - Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute
431 (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
432 by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
434 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
435 supported in any clocked block.
437 - The syntax ``@($global_clock)`` can be used to create FFs that have no
438 explicit clock input ($ff cells). The same can be achieved by using
439 ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
440 is marked with the ``(* gclk *)`` Verilog attribute.
443 Supported features from SystemVerilog
444 =====================================
446 When ``read_verilog`` is called with ``-sv``, it accepts some language features
449 - The ``assert`` statement from SystemVerilog is supported in its most basic
450 form. In module context: ``assert property (<expression>);`` and within an
451 always block: ``assert(<expression>);``. It is transformed to a $assert cell.
453 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
454 also supported. The same limitations as with the ``assert`` statement apply.
456 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
457 and ``bit`` are supported.
459 - Declaring free variables with ``rand`` and ``rand const`` is supported.
461 - Checkers without a port list that do not need to be instantiated (but instead
462 behave like a named block) are supported.
464 - SystemVerilog packages are supported. Once a SystemVerilog file is read
465 into a design with ``read_verilog``, all its packages are available to
466 SystemVerilog files being read into the same design afterwards.
468 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
469 ports are inputs or outputs are supported.
472 Building the documentation
473 ==========================
475 Note that there is no need to build the manual if you just want to read it.
476 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
479 On Ubuntu, texlive needs these packages to be able to build the manual:
481 sudo apt-get install texlive-binaries
482 sudo apt-get install texlive-science # install algorithm2e.sty
483 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
484 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
485 sudo apt-get install texlive-publishers # IEEEtran.cls
487 Also the non-free font luximono should be installed, there is unfortunately
488 no Ubuntu package for this so it should be installed separately using
491 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
492 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
493 getnonfreefonts luximono # installs to /home/user/texmf
495 Then execute, from the root of the repository:
501 - To run `make manual` you need to have installed Yosys with `make install`,
502 otherwise it will fail on finding `kernel/yosys.h` while building