2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
37 Web Site and Other Resources
38 ============================
40 More information and documentation can be found on the Yosys web site:
41 - http://www.clifford.at/yosys/
43 The "Documentation" page on the web site contains links to more resources,
44 including a manual that even describes some of the Yosys internals:
45 - http://www.clifford.at/yosys/documentation.html
47 The file `CodingReadme` in this directory contains additional information
48 for people interested in using the Yosys C++ APIs.
50 Users interested in formal verification might want to use the formal verification
51 front-end for Yosys, SymbiYosys:
52 - https://symbiyosys.readthedocs.io/en/latest/
53 - https://github.com/YosysHQ/SymbiYosys
59 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
60 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
61 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
62 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
64 For example on Ubuntu Linux 16.04 LTS the following commands will install all
65 prerequisites for building yosys:
67 $ sudo apt-get install build-essential clang bison flex \
68 libreadline-dev gawk tcl-dev libffi-dev git \
69 graphviz xdot pkg-config python3 libboost-system-dev \
70 libboost-python-dev libboost-filesystem-dev zlib1g-dev
72 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
74 $ brew tap Homebrew/bundle && brew bundle
75 $ sudo port install bison flex readline gawk libffi \
76 git graphviz pkgconfig python36 boost zlib
78 On FreeBSD use the following command to install all prerequisites:
80 # pkg install bison flex readline gawk libffi\
81 git graphviz pkgconf python3 python36 tcl-wrapper boost-libs
83 On FreeBSD system use gmake instead of make. To run tests use:
84 % MAKE=gmake CC=cc gmake test
86 For Cygwin use the following command to install all prerequisites, or select these additional packages:
88 setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel
90 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
91 as a source distribution for Visual Studio. Visit the Yosys download page for
92 more information: http://www.clifford.at/yosys/download.html
94 To configure the build system to use a specific compiler, use one of
99 For other compilers and build configurations it might be
100 necessary to make some changes to the config section of the
103 $ vi Makefile # ..or..
106 To build Yosys simply type 'make' in this directory.
111 Note that this also downloads, builds and installs ABC (using yosys-abc
114 Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:
121 Yosys can be used with the interactive command shell, with
122 synthesis scripts or with command line arguments. Let's perform
123 a simple synthesis job using the interactive command shell:
128 the command ``help`` can be used to print a list of all available
129 commands and ``help <command>`` to print details on the specified command:
133 reading and elaborating the design using the Verilog frontend:
135 yosys> read -sv tests/simple/fiedler-cooley.v
136 yosys> hierarchy -top up3down5
138 writing the design to the console in Yosys's internal format:
142 convert processes (``always`` blocks) to netlist elements and perform
143 some simple optimizations:
147 display design netlist using ``xdot``:
151 the same thing using ``gv`` as postscript viewer:
153 yosys> show -format ps -viewer gv
155 translating netlist to gate logic and perform some simple optimizations:
159 write design netlist to a new Verilog file:
161 yosys> write_verilog synth.v
163 or using a simple synthesis script:
166 read -sv tests/simple/fiedler-cooley.v
167 hierarchy -top up3down5
168 proc; opt; techmap; opt
169 write_verilog synth.v
173 If ABC is enabled in the Yosys build configuration and a cell library is given
174 in the liberty file ``mycells.lib``, the following synthesis script will
175 synthesize for the given cell library:
178 read -sv tests/simple/fiedler-cooley.v
179 hierarchy -top up3down5
181 # the high-level stuff
182 proc; fsm; opt; memory; opt
184 # mapping to internal cell library
187 # mapping flip-flops to mycells.lib
188 dfflibmap -liberty mycells.lib
190 # mapping logic to mycells.lib
191 abc -liberty mycells.lib
196 If you do not have a liberty file but want to test this synthesis script,
197 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources
200 Liberty file downloads for and information about free and open ASIC standard
201 cell libraries can be found here:
203 - http://www.vlsitechnology.org/html/libraries.html
204 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
206 The command ``synth`` provides a good default synthesis script (see
209 read -sv tests/simple/fiedler-cooley.v
212 # mapping to target cells
213 dfflibmap -liberty mycells.lib
214 abc -liberty mycells.lib
217 The command ``prep`` provides a good default word-level synthesis script, as
218 used in SMT-based formal verification.
221 Unsupported Verilog-2005 Features
222 =================================
224 The following Verilog-2005 features are not supported by
225 Yosys and there are currently no plans to add support
228 - Non-synthesizable language features as defined in
229 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
231 - The ``tri``, ``triand`` and ``trior`` net types
233 - The ``config`` and ``disable`` keywords and library map files
236 Verilog Attributes and non-standard features
237 ============================================
239 - The ``full_case`` attribute on case statements is supported
240 (also the non-standard ``// synopsys full_case`` directive)
242 - The ``parallel_case`` attribute on case statements is supported
243 (also the non-standard ``// synopsys parallel_case`` directive)
245 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
246 directives are also supported (but the use of ``` `ifdef .. `endif ```
247 is strongly recommended instead).
249 - The ``nomem2reg`` attribute on modules or arrays prohibits the
250 automatic early conversion of arrays to separate registers. This
251 is potentially dangerous. Usually the front-end has good reasons
252 for converting an array to a list of registers. Prohibiting this
253 step will likely result in incorrect synthesis results.
255 - The ``mem2reg`` attribute on modules or arrays forces the early
256 conversion of arrays to separate registers.
258 - The ``nomeminit`` attribute on modules or arrays prohibits the
259 creation of initialized memories. This effectively puts ``mem2reg``
260 on all memories that are written to in an ``initial`` block and
263 - The ``nolatches`` attribute on modules or always-blocks
264 prohibits the generation of logic-loops for latches. Instead
265 all not explicitly assigned values default to x-bits. This does
266 not affect clocked storage elements such as flip-flops.
268 - The ``nosync`` attribute on registers prohibits the generation of a
269 storage element. The register itself will always have all bits set
270 to 'x' (undefined). The variable may only be used as blocking assigned
271 temporary variable within an always block. This is mostly used internally
272 by Yosys to synthesize Verilog functions and access arrays.
274 - The ``onehot`` attribute on wires mark them as one-hot state register. This
275 is used for example for memory port sharing and set by the fsm_map pass.
277 - The ``blackbox`` attribute on modules is used to mark empty stub modules
278 that have the same ports as the real thing but do not contain information
279 on the internal configuration. This modules are only used by the synthesis
280 passes to identify input and output ports of cells. The Verilog backend
281 also does not output blackbox modules on default. ``read_verilog``, unless
282 called with ``-noblackbox`` will automatically set the blackbox attribute
283 on any empty module it reads.
285 - The ``noblackbox`` attribute set on an empty module prevents ``read_verilog``
286 from automatically setting the blackbox attribute on the module.
288 - The ``whitebox`` attribute on modules triggers the same behavior as
289 ``blackbox``, but is for whitebox modules, i.e. library modules that
290 contain a behavioral model of the cell type.
292 - The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog``
293 is run in `-lib` mode. Otherwise it's automatically removed.
295 - The ``dynports`` attribute is used by the Verilog front-end to mark modules
296 that have ports with a width that depends on a parameter.
298 - The ``hdlname`` attribute is used by some passes to document the original
299 (HDL) name of a module when renaming a module.
301 - The ``keep`` attribute on cells and wires is used to mark objects that should
302 never be removed by the optimizer. This is used for example for cells that
303 have hidden connections that are not part of the netlist, such as IO pads.
304 Setting the ``keep`` attribute on a module has the same effect as setting it
305 on all instances of the module.
307 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
308 command from flattening the indicated cells and modules.
310 - The ``init`` attribute on wires is set by the frontend when a register is
311 initialized "FPGA-style" with ``reg foo = val``. It can be used during
312 synthesis to add the necessary reset logic.
314 - The ``top`` attribute on a module marks this module as the top of the
315 design hierarchy. The ``hierarchy`` command sets this attribute when called
316 with ``-top``. Other commands, such as ``flatten`` and various backends
317 use this attribute to determine the top module.
319 - The ``src`` attribute is set on cells and wires created by to the string
320 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
321 through the synthesis. When entities are combined, a new |-separated
322 string is created that contains all the string from the original entities.
324 - The ``defaultvalue`` attribute is used to store default values for
325 module inputs. The attribute is attached to the input wire by the HDL
326 front-end when the input is declared with a default value.
328 - The ``parameter`` and ``localparam`` attributes are used to mark wires
329 that represent module parameters or localparams (when the HDL front-end
330 is run in -pwires mode).
332 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
333 the non-standard ``{* ... *}`` attribute syntax to set default attributes
334 for everything that comes after the ``{* ... *}`` statement. (Reset
335 by adding an empty ``{* *}`` statement.)
337 - In module parameter and port declarations, and cell port and parameter
338 lists, a trailing comma is ignored. This simplifies writing Verilog code
339 generators a bit in some cases.
341 - Modules can be declared with ``module mod_name(...);`` (with three dots
342 instead of a list of module ports). With this syntax it is sufficient
343 to simply declare a module port as 'input' or 'output' in the module
346 - When defining a macro with `define, all text between triple double quotes
347 is interpreted as macro body, even if it contains unescaped newlines. The
348 triple double quotes are removed from the macro body. For example:
350 `define MY_MACRO(a, b) """
355 - The attribute ``via_celltype`` can be used to implement a Verilog task or
356 function by instantiating the specified cell type. The value is the name
357 of the cell type to use. For functions the name of the output port can
358 be specified by appending it to the cell type separated by a whitespace.
359 The body of the task or function is unused in this case and can be used
360 to specify a behavioral model of the cell type for simulation. For example:
362 module my_add3(A, B, C, Y);
364 input [WIDTH-1:0] A, B, C;
365 output [WIDTH-1:0] Y;
371 (* via_celltype = "my_add3 Y" *)
372 (* via_celltype_defparam_WIDTH = 32 *)
373 function [31:0] add3;
374 input [31:0] A, B, C;
382 - A limited subset of DPI-C functions is supported. The plugin mechanism
383 (see ``help plugin``) can be used to load .so files with implementations
384 of DPI-C routines. As a non-standard extension it is possible to specify
385 a plugin alias using the ``<alias>:`` syntax. For example:
388 import "DPI-C" function foo:round = real my_round (real);
389 parameter real r = my_round(12.345);
392 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
394 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
395 expressions as ``<size>``. If the expression is not a simple identifier, it
396 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
398 - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in
399 initial blocks in an unconditional context (only if/case statements on
400 expressions over parameters and constant values are allowed). The intended
401 use for this is synthesis-time DRC.
403 - There is limited support for converting specify .. endspecify statements to
404 special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in
405 blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
406 functionality. (By default specify .. endspecify blocks are ignored.)
408 - The module attribute ``abc_box_id`` specifies a positive integer linking a
409 blackbox or whitebox definition to a corresponding entry in a `abc9`
412 - The port attribute ``abc_carry`` marks the carry-in (if an input port) and
413 carry-out (if output port) ports of a box. This information is necessary for
414 `abc9` to preserve the integrity of carry-chains. Specifying this attribute
415 onto a bus port will affect only its most significant bit.
417 - The port attribute ``abc_arrival`` specifies an integer (for output ports
418 only) to be used as the arrival time of this sequential port. It can be used,
419 for example, to specify the clk-to-Q delay of a flip-flop for consideration
423 Non-standard or SystemVerilog features for formal verification
424 ==============================================================
426 - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
427 when ``read_verilog`` is called with ``-formal``.
429 - The system task ``$initstate`` evaluates to 1 in the initial state and
432 - The system function ``$anyconst`` evaluates to any constant value. This is
433 equivalent to declaring a reg as ``rand const``, but also works outside
434 of checkers. (Yosys also supports ``rand const`` outside checkers.)
436 - The system function ``$anyseq`` evaluates to any value, possibly a different
437 value in each cycle. This is equivalent to declaring a reg as ``rand``,
438 but also works outside of checkers. (Yosys also supports ``rand``
439 variables outside checkers.)
441 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
442 formal exist-forall problems. Assumptions only hold if the trace satisfies
443 the assumption for all ``$allconst/$allseq`` values. For assertions and cover
444 statements it is sufficient if just one ``$allconst/$allseq`` value triggers
445 the property (similar to ``$anyconst/$anyseq``).
447 - Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute
448 (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
449 by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
451 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
452 supported in any clocked block.
454 - The syntax ``@($global_clock)`` can be used to create FFs that have no
455 explicit clock input (``$ff`` cells). The same can be achieved by using
456 ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
457 is marked with the ``(* gclk *)`` Verilog attribute.
460 Supported features from SystemVerilog
461 =====================================
463 When ``read_verilog`` is called with ``-sv``, it accepts some language features
466 - The ``assert`` statement from SystemVerilog is supported in its most basic
467 form. In module context: ``assert property (<expression>);`` and within an
468 always block: ``assert(<expression>);``. It is transformed to an ``$assert`` cell.
470 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
471 also supported. The same limitations as with the ``assert`` statement apply.
473 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
474 and ``bit`` are supported.
476 - Declaring free variables with ``rand`` and ``rand const`` is supported.
478 - Checkers without a port list that do not need to be instantiated (but instead
479 behave like a named block) are supported.
481 - SystemVerilog packages are supported. Once a SystemVerilog file is read
482 into a design with ``read_verilog``, all its packages are available to
483 SystemVerilog files being read into the same design afterwards.
485 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
486 ports are inputs or outputs are supported.
489 Building the documentation
490 ==========================
492 Note that there is no need to build the manual if you just want to read it.
493 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
496 On Ubuntu, texlive needs these packages to be able to build the manual:
498 sudo apt-get install texlive-binaries
499 sudo apt-get install texlive-science # install algorithm2e.sty
500 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
501 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
502 sudo apt-get install texlive-publishers # IEEEtran.cls
504 Also the non-free font luximono should be installed, there is unfortunately
505 no Ubuntu package for this so it should be installed separately using
508 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
509 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
510 getnonfreefonts luximono # installs to /home/user/texmf
512 Then execute, from the root of the repository:
518 - To run `make manual` you need to have installed Yosys with `make install`,
519 otherwise it will fail on finding `kernel/yosys.h` while building