2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
37 Web Site and Other Resources
38 ============================
40 More information and documentation can be found on the Yosys web site:
41 - http://www.clifford.at/yosys/
43 The "Documentation" page on the web site contains links to more resources,
44 including a manual that even describes some of the Yosys internals:
45 - http://www.clifford.at/yosys/documentation.html
47 The file `CodingReadme` in this directory contains additional information
48 for people interested in using the Yosys C++ APIs.
50 Users interested in formal verification might want to use the formal verification
51 front-end for Yosys, SymbiYosys:
52 - https://symbiyosys.readthedocs.io/en/latest/
53 - https://github.com/YosysHQ/SymbiYosys
59 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
60 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
61 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
62 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
64 For example on Ubuntu Linux 16.04 LTS the following commands will install all
65 prerequisites for building yosys:
67 $ sudo apt-get install build-essential clang bison flex \
68 libreadline-dev gawk tcl-dev libffi-dev git \
69 graphviz xdot pkg-config python3 libboost-system-dev \
70 libboost-python-dev libboost-filesystem-dev
72 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
74 $ brew tap Homebrew/bundle && brew bundle
75 $ sudo port install bison flex readline gawk libffi \
76 git graphviz pkgconfig python36 boost
78 On FreeBSD use the following command to install all prerequisites:
80 # pkg install bison flex readline gawk libffi\
81 git graphviz pkgconfig python3 python36 tcl-wrapper boost-libs
83 On FreeBSD system use gmake instead of make. To run tests use:
84 % MAKE=gmake CC=cc gmake test
86 For Cygwin use the following command to install all prerequisites, or select these additional packages:
88 setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build
90 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
91 as a source distribution for Visual Studio. Visit the Yosys download page for
92 more information: http://www.clifford.at/yosys/download.html
94 To configure the build system to use a specific compiler, use one of
99 For other compilers and build configurations it might be
100 necessary to make some changes to the config section of the
103 $ vi Makefile # ..or..
106 To build Yosys simply type 'make' in this directory.
111 Note that this also downloads, builds and installs ABC (using yosys-abc
114 Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:
121 Yosys can be used with the interactive command shell, with
122 synthesis scripts or with command line arguments. Let's perform
123 a simple synthesis job using the interactive command shell:
128 the command ``help`` can be used to print a list of all available
129 commands and ``help <command>`` to print details on the specified command:
133 reading the design using the Verilog frontend:
135 yosys> read_verilog tests/simple/fiedler-cooley.v
137 writing the design to the console in Yosys's internal format:
141 elaborate design hierarchy:
145 convert processes (``always`` blocks) to netlist elements and perform
146 some simple optimizations:
150 display design netlist using ``xdot``:
154 the same thing using ``gv`` as postscript viewer:
156 yosys> show -format ps -viewer gv
158 translating netlist to gate logic and perform some simple optimizations:
162 write design netlist to a new Verilog file:
164 yosys> write_verilog synth.v
166 a similar synthesis can be performed using yosys command line options only:
168 $ ./yosys -o synth.v -p hierarchy -p proc -p opt \
169 -p techmap -p opt tests/simple/fiedler-cooley.v
171 or using a simple synthesis script:
174 read_verilog tests/simple/fiedler-cooley.v
175 hierarchy; proc; opt; techmap; opt
176 write_verilog synth.v
180 It is also possible to only have the synthesis commands but not the read/write
181 commands in the synthesis script:
184 hierarchy; proc; opt; techmap; opt
186 $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys
188 The following very basic synthesis script should work well with all designs:
190 # check design hierarchy
193 # translate processes (always blocks)
196 # detect and optimize FSM encodings
199 # implement memories (arrays)
202 # convert to gate logic
205 If ABC is enabled in the Yosys build configuration and a cell library is given
206 in the liberty file ``mycells.lib``, the following synthesis script will
207 synthesize for the given cell library:
209 # the high-level stuff
210 hierarchy; proc; fsm; opt; memory; opt
212 # mapping to internal cell library
215 # mapping flip-flops to mycells.lib
216 dfflibmap -liberty mycells.lib
218 # mapping logic to mycells.lib
219 abc -liberty mycells.lib
224 If you do not have a liberty file but want to test this synthesis script,
225 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources.
227 Liberty file downloads for and information about free and open ASIC standard
228 cell libraries can be found here:
230 - http://www.vlsitechnology.org/html/libraries.html
231 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
233 The command ``synth`` provides a good default synthesis script (see
234 ``help synth``). If possible a synthesis script should borrow from ``synth``.
237 # the high-level stuff
241 # mapping to internal cells
243 dfflibmap -liberty mycells.lib
244 abc -liberty mycells.lib
247 Yosys is under construction. A more detailed documentation will follow.
250 Unsupported Verilog-2005 Features
251 =================================
253 The following Verilog-2005 features are not supported by
254 Yosys and there are currently no plans to add support
257 - Non-synthesizable language features as defined in
258 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
260 - The ``tri``, ``triand`` and ``trior`` net types
262 - The ``config`` and ``disable`` keywords and library map files
265 Verilog Attributes and non-standard features
266 ============================================
268 - The ``full_case`` attribute on case statements is supported
269 (also the non-standard ``// synopsys full_case`` directive)
271 - The ``parallel_case`` attribute on case statements is supported
272 (also the non-standard ``// synopsys parallel_case`` directive)
274 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
275 directives are also supported (but the use of ``` `ifdef .. `endif ```
276 is strongly recommended instead).
278 - The ``nomem2reg`` attribute on modules or arrays prohibits the
279 automatic early conversion of arrays to separate registers. This
280 is potentially dangerous. Usually the front-end has good reasons
281 for converting an array to a list of registers. Prohibiting this
282 step will likely result in incorrect synthesis results.
284 - The ``mem2reg`` attribute on modules or arrays forces the early
285 conversion of arrays to separate registers.
287 - The ``nomeminit`` attribute on modules or arrays prohibits the
288 creation of initialized memories. This effectively puts ``mem2reg``
289 on all memories that are written to in an ``initial`` block and
292 - The ``nolatches`` attribute on modules or always-blocks
293 prohibits the generation of logic-loops for latches. Instead
294 all not explicitly assigned values default to x-bits. This does
295 not affect clocked storage elements such as flip-flops.
297 - The ``nosync`` attribute on registers prohibits the generation of a
298 storage element. The register itself will always have all bits set
299 to 'x' (undefined). The variable may only be used as blocking assigned
300 temporary variable within an always block. This is mostly used internally
301 by Yosys to synthesize Verilog functions and access arrays.
303 - The ``onehot`` attribute on wires mark them as one-hot state register. This
304 is used for example for memory port sharing and set by the fsm_map pass.
306 - The ``blackbox`` attribute on modules is used to mark empty stub modules
307 that have the same ports as the real thing but do not contain information
308 on the internal configuration. This modules are only used by the synthesis
309 passes to identify input and output ports of cells. The Verilog backend
310 also does not output blackbox modules on default. ``read_verilog``, unless
311 called with ``-noblackbox`` will automatically set the blackbox attribute
312 on any empty module it reads.
314 - The ``noblackbox`` attribute set on an empty module prevents ``read_verilog``
315 from automatically setting the blackbox attribute on the module.
317 - The ``whitebox`` attribute on modules triggers the same behavior as
318 ``blackbox``, but is for whitebox modules, i.e. library modules that
319 contain a behavioral model of the cell type.
321 - The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog``
322 is run in `-lib` mode. Otherwise it's automatically removed.
324 - The ``dynports`` attribute is used by the Verilog front-end to mark modules
325 that have ports with a width that depends on a parameter.
327 - The ``hdlname`` attribute is used by some passes to document the original
328 (HDL) name of a module when renaming a module.
330 - The ``keep`` attribute on cells and wires is used to mark objects that should
331 never be removed by the optimizer. This is used for example for cells that
332 have hidden connections that are not part of the netlist, such as IO pads.
333 Setting the ``keep`` attribute on a module has the same effect as setting it
334 on all instances of the module.
336 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
337 command from flattening the indicated cells and modules.
339 - The ``init`` attribute on wires is set by the frontend when a register is
340 initialized "FPGA-style" with ``reg foo = val``. It can be used during
341 synthesis to add the necessary reset logic.
343 - The ``top`` attribute on a module marks this module as the top of the
344 design hierarchy. The ``hierarchy`` command sets this attribute when called
345 with ``-top``. Other commands, such as ``flatten`` and various backends
346 use this attribute to determine the top module.
348 - The ``src`` attribute is set on cells and wires created by to the string
349 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
350 through the synthesis. When entities are combined, a new |-separated
351 string is created that contains all the string from the original entities.
353 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
354 the non-standard ``{* ... *}`` attribute syntax to set default attributes
355 for everything that comes after the ``{* ... *}`` statement. (Reset
356 by adding an empty ``{* *}`` statement.)
358 - In module parameter and port declarations, and cell port and parameter
359 lists, a trailing comma is ignored. This simplifies writing Verilog code
360 generators a bit in some cases.
362 - Modules can be declared with ``module mod_name(...);`` (with three dots
363 instead of a list of module ports). With this syntax it is sufficient
364 to simply declare a module port as 'input' or 'output' in the module
367 - When defining a macro with `define, all text between triple double quotes
368 is interpreted as macro body, even if it contains unescaped newlines. The
369 triple double quotes are removed from the macro body. For example:
371 `define MY_MACRO(a, b) """
376 - The attribute ``via_celltype`` can be used to implement a Verilog task or
377 function by instantiating the specified cell type. The value is the name
378 of the cell type to use. For functions the name of the output port can
379 be specified by appending it to the cell type separated by a whitespace.
380 The body of the task or function is unused in this case and can be used
381 to specify a behavioral model of the cell type for simulation. For example:
383 module my_add3(A, B, C, Y);
385 input [WIDTH-1:0] A, B, C;
386 output [WIDTH-1:0] Y;
392 (* via_celltype = "my_add3 Y" *)
393 (* via_celltype_defparam_WIDTH = 32 *)
394 function [31:0] add3;
395 input [31:0] A, B, C;
403 - A limited subset of DPI-C functions is supported. The plugin mechanism
404 (see ``help plugin``) can be used to load .so files with implementations
405 of DPI-C routines. As a non-standard extension it is possible to specify
406 a plugin alias using the ``<alias>:`` syntax. For example:
409 import "DPI-C" function foo:round = real my_round (real);
410 parameter real r = my_round(12.345);
413 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
415 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
416 expressions as <size>. If the expression is not a simple identifier, it
417 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
419 - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in
420 initial blocks in an unconditional context (only if/case statements on
421 expressions over parameters and constant values are allowed). The intended
422 use for this is synthesis-time DRC.
424 - There is limited support for converting specify .. endspecify statements to
425 special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in
426 blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
427 functionality. (By default specify .. endspecify blocks are ignored.)
430 Non-standard or SystemVerilog features for formal verification
431 ==============================================================
433 - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
434 when ``read_verilog`` is called with ``-formal``.
436 - The system task ``$initstate`` evaluates to 1 in the initial state and
439 - The system function ``$anyconst`` evaluates to any constant value. This is
440 equivalent to declaring a reg as ``rand const``, but also works outside
441 of checkers. (Yosys also supports ``rand const`` outside checkers.)
443 - The system function ``$anyseq`` evaluates to any value, possibly a different
444 value in each cycle. This is equivalent to declaring a reg as ``rand``,
445 but also works outside of checkers. (Yosys also supports ``rand``
446 variables outside checkers.)
448 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
449 formal exist-forall problems. Assumptions only hold if the trace satisfies
450 the assumption for all ``$allconst/$allseq`` values. For assertions and cover
451 statements it is sufficient if just one ``$allconst/$allseq`` value triggers
452 the property (similar to ``$anyconst/$anyseq``).
454 - Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute
455 (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
456 by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
458 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
459 supported in any clocked block.
461 - The syntax ``@($global_clock)`` can be used to create FFs that have no
462 explicit clock input (``$ff`` cells). The same can be achieved by using
463 ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
464 is marked with the ``(* gclk *)`` Verilog attribute.
467 Supported features from SystemVerilog
468 =====================================
470 When ``read_verilog`` is called with ``-sv``, it accepts some language features
473 - The ``assert`` statement from SystemVerilog is supported in its most basic
474 form. In module context: ``assert property (<expression>);`` and within an
475 always block: ``assert(<expression>);``. It is transformed to an ``$assert`` cell.
477 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
478 also supported. The same limitations as with the ``assert`` statement apply.
480 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
481 and ``bit`` are supported.
483 - Declaring free variables with ``rand`` and ``rand const`` is supported.
485 - Checkers without a port list that do not need to be instantiated (but instead
486 behave like a named block) are supported.
488 - SystemVerilog packages are supported. Once a SystemVerilog file is read
489 into a design with ``read_verilog``, all its packages are available to
490 SystemVerilog files being read into the same design afterwards.
492 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
493 ports are inputs or outputs are supported.
496 Building the documentation
497 ==========================
499 Note that there is no need to build the manual if you just want to read it.
500 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
503 On Ubuntu, texlive needs these packages to be able to build the manual:
505 sudo apt-get install texlive-binaries
506 sudo apt-get install texlive-science # install algorithm2e.sty
507 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
508 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
509 sudo apt-get install texlive-publishers # IEEEtran.cls
511 Also the non-free font luximono should be installed, there is unfortunately
512 no Ubuntu package for this so it should be installed separately using
515 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
516 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
517 getnonfreefonts luximono # installs to /home/user/texmf
519 Then execute, from the root of the repository:
525 - To run `make manual` you need to have installed Yosys with `make install`,
526 otherwise it will fail on finding `kernel/yosys.h` while building