2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
37 Web Site and Other Resources
38 ============================
40 More information and documentation can be found on the Yosys web site:
41 - http://www.clifford.at/yosys/
43 The "Documentation" page on the web site contains links to more resources,
44 including a manual that even describes some of the Yosys internals:
45 - http://www.clifford.at/yosys/documentation.html
47 The file `CodingReadme` in this directory contains additional information
48 for people interested in using the Yosys C++ APIs.
50 Users interested in formal verification might want to use the formal verification
51 front-end for Yosys, SymbiYosys:
52 - https://symbiyosys.readthedocs.io/en/latest/
53 - https://github.com/YosysHQ/SymbiYosys
59 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
60 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
61 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
62 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
64 For example on Ubuntu Linux 16.04 LTS the following commands will install all
65 prerequisites for building yosys:
67 $ sudo apt-get install build-essential clang bison flex \
68 libreadline-dev gawk tcl-dev libffi-dev git \
69 graphviz xdot pkg-config python3
71 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
73 $ brew tap Homebrew/bundle && brew bundle
74 $ sudo port install bison flex readline gawk libffi \
75 git graphviz pkgconfig python36
77 On FreeBSD use the following command to install all prerequisites:
79 # pkg install bison flex readline gawk libffi\
80 git graphviz pkgconfig python3 python36 tcl-wrapper
82 On FreeBSD system use gmake instead of make. To run tests use:
83 % MAKE=gmake CC=cc gmake test
85 For Cygwin use the following command to install all prerequisites, or select these additional packages:
87 setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel
89 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
90 as a source distribution for Visual Studio. Visit the Yosys download page for
91 more information: http://www.clifford.at/yosys/download.html
93 To configure the build system to use a specific compiler, use one of
98 For other compilers and build configurations it might be
99 necessary to make some changes to the config section of the
102 $ vi Makefile # ..or..
105 To build Yosys simply type 'make' in this directory.
110 Note that this also downloads, builds and installs ABC (using yosys-abc
113 Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:
120 Yosys can be used with the interactive command shell, with
121 synthesis scripts or with command line arguments. Let's perform
122 a simple synthesis job using the interactive command shell:
127 the command ``help`` can be used to print a list of all available
128 commands and ``help <command>`` to print details on the specified command:
132 reading the design using the Verilog frontend:
134 yosys> read_verilog tests/simple/fiedler-cooley.v
136 writing the design to the console in Yosys's internal format:
140 elaborate design hierarchy:
144 convert processes (``always`` blocks) to netlist elements and perform
145 some simple optimizations:
149 display design netlist using ``xdot``:
153 the same thing using ``gv`` as postscript viewer:
155 yosys> show -format ps -viewer gv
157 translating netlist to gate logic and perform some simple optimizations:
161 write design netlist to a new Verilog file:
163 yosys> write_verilog synth.v
165 a similar synthesis can be performed using yosys command line options only:
167 $ ./yosys -o synth.v -p hierarchy -p proc -p opt \
168 -p techmap -p opt tests/simple/fiedler-cooley.v
170 or using a simple synthesis script:
173 read_verilog tests/simple/fiedler-cooley.v
174 hierarchy; proc; opt; techmap; opt
175 write_verilog synth.v
179 It is also possible to only have the synthesis commands but not the read/write
180 commands in the synthesis script:
183 hierarchy; proc; opt; techmap; opt
185 $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys
187 The following very basic synthesis script should work well with all designs:
189 # check design hierarchy
192 # translate processes (always blocks)
195 # detect and optimize FSM encodings
198 # implement memories (arrays)
201 # convert to gate logic
204 If ABC is enabled in the Yosys build configuration and a cell library is given
205 in the liberty file ``mycells.lib``, the following synthesis script will
206 synthesize for the given cell library:
208 # the high-level stuff
209 hierarchy; proc; fsm; opt; memory; opt
211 # mapping to internal cell library
214 # mapping flip-flops to mycells.lib
215 dfflibmap -liberty mycells.lib
217 # mapping logic to mycells.lib
218 abc -liberty mycells.lib
223 If you do not have a liberty file but want to test this synthesis script,
224 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources.
226 Liberty file downloads for and information about free and open ASIC standard
227 cell libraries can be found here:
229 - http://www.vlsitechnology.org/html/libraries.html
230 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
232 The command ``synth`` provides a good default synthesis script (see
233 ``help synth``). If possible a synthesis script should borrow from ``synth``.
236 # the high-level stuff
240 # mapping to internal cells
242 dfflibmap -liberty mycells.lib
243 abc -liberty mycells.lib
246 Yosys is under construction. A more detailed documentation will follow.
249 Unsupported Verilog-2005 Features
250 =================================
252 The following Verilog-2005 features are not supported by
253 Yosys and there are currently no plans to add support
256 - Non-synthesizable language features as defined in
257 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
259 - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
261 - The ``config`` keyword and library map files
263 - The ``disable``, ``primitive`` and ``specify`` statements
265 - Latched logic (is synthesized as logic with feedback loops)
268 Verilog Attributes and non-standard features
269 ============================================
271 - The ``full_case`` attribute on case statements is supported
272 (also the non-standard ``// synopsys full_case`` directive)
274 - The ``parallel_case`` attribute on case statements is supported
275 (also the non-standard ``// synopsys parallel_case`` directive)
277 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
278 directives are also supported (but the use of ``` `ifdef .. `endif ```
279 is strongly recommended instead).
281 - The ``nomem2reg`` attribute on modules or arrays prohibits the
282 automatic early conversion of arrays to separate registers. This
283 is potentially dangerous. Usually the front-end has good reasons
284 for converting an array to a list of registers. Prohibiting this
285 step will likely result in incorrect synthesis results.
287 - The ``mem2reg`` attribute on modules or arrays forces the early
288 conversion of arrays to separate registers.
290 - The ``nomeminit`` attribute on modules or arrays prohibits the
291 creation of initialized memories. This effectively puts ``mem2reg``
292 on all memories that are written to in an ``initial`` block and
295 - The ``nolatches`` attribute on modules or always-blocks
296 prohibits the generation of logic-loops for latches. Instead
297 all not explicitly assigned values default to x-bits. This does
298 not affect clocked storage elements such as flip-flops.
300 - The ``nosync`` attribute on registers prohibits the generation of a
301 storage element. The register itself will always have all bits set
302 to 'x' (undefined). The variable may only be used as blocking assigned
303 temporary variable within an always block. This is mostly used internally
304 by Yosys to synthesize Verilog functions and access arrays.
306 - The ``onehot`` attribute on wires mark them as one-hot state register. This
307 is used for example for memory port sharing and set by the fsm_map pass.
309 - The ``blackbox`` attribute on modules is used to mark empty stub modules
310 that have the same ports as the real thing but do not contain information
311 on the internal configuration. This modules are only used by the synthesis
312 passes to identify input and output ports of cells. The Verilog backend
313 also does not output blackbox modules on default. ``read_verilog``, unless
314 called with ``-noblackbox`` will automatically set the blackbox attribute
315 on any empty module it reads.
317 - The ``noblackbox`` attribute set on an empty module prevents ``read_verilog``
318 from automatically setting the blackbox attribute on the module.
320 - The ``whitebox`` attribute on modules triggers the same behavior as
321 ``blackbox``, but is for whitebox modules, i.e. library modules that
322 contain a behavioral model of the cell type.
324 - The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog``
325 is run in `-lib` mode. Otherwise it's automatically removed.
327 - The ``dynports`` attribute is used by the Verilog front-end to mark modules
328 that have ports with a width that depends on a parameter.
330 - The ``hdlname`` attribute is used by some passes to document the original
331 (HDL) name of a module when renaming a module.
333 - The ``keep`` attribute on cells and wires is used to mark objects that should
334 never be removed by the optimizer. This is used for example for cells that
335 have hidden connections that are not part of the netlist, such as IO pads.
336 Setting the ``keep`` attribute on a module has the same effect as setting it
337 on all instances of the module.
339 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
340 command from flattening the indicated cells and modules.
342 - The ``init`` attribute on wires is set by the frontend when a register is
343 initialized "FPGA-style" with ``reg foo = val``. It can be used during
344 synthesis to add the necessary reset logic.
346 - The ``top`` attribute on a module marks this module as the top of the
347 design hierarchy. The ``hierarchy`` command sets this attribute when called
348 with ``-top``. Other commands, such as ``flatten`` and various backends
349 use this attribute to determine the top module.
351 - The ``src`` attribute is set on cells and wires created by to the string
352 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
353 through the synthesis. When entities are combined, a new |-separated
354 string is created that contains all the string from the original entities.
356 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
357 the non-standard ``{* ... *}`` attribute syntax to set default attributes
358 for everything that comes after the ``{* ... *}`` statement. (Reset
359 by adding an empty ``{* *}`` statement.)
361 - In module parameter and port declarations, and cell port and parameter
362 lists, a trailing comma is ignored. This simplifies writing Verilog code
363 generators a bit in some cases.
365 - Modules can be declared with ``module mod_name(...);`` (with three dots
366 instead of a list of module ports). With this syntax it is sufficient
367 to simply declare a module port as 'input' or 'output' in the module
370 - When defining a macro with `define, all text between triple double quotes
371 is interpreted as macro body, even if it contains unescaped newlines. The
372 tipple double quotes are removed from the macro body. For example:
374 `define MY_MACRO(a, b) """
379 - The attribute ``via_celltype`` can be used to implement a Verilog task or
380 function by instantiating the specified cell type. The value is the name
381 of the cell type to use. For functions the name of the output port can
382 be specified by appending it to the cell type separated by a whitespace.
383 The body of the task or function is unused in this case and can be used
384 to specify a behavioral model of the cell type for simulation. For example:
386 module my_add3(A, B, C, Y);
388 input [WIDTH-1:0] A, B, C;
389 output [WIDTH-1:0] Y;
395 (* via_celltype = "my_add3 Y" *)
396 (* via_celltype_defparam_WIDTH = 32 *)
397 function [31:0] add3;
398 input [31:0] A, B, C;
406 - A limited subset of DPI-C functions is supported. The plugin mechanism
407 (see ``help plugin``) can be used to load .so files with implementations
408 of DPI-C routines. As a non-standard extension it is possible to specify
409 a plugin alias using the ``<alias>:`` syntax. For example:
412 import "DPI-C" function foo:round = real my_round (real);
413 parameter real r = my_round(12.345);
416 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
418 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
419 expressions as <size>. If the expression is not a simple identifier, it
420 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
422 - The system tasks ``$finish`` and ``$display`` are supported in initial blocks
423 in an unconditional context (only if/case statements on parameters
424 and constant values). The intended use for this is synthesis-time DRC.
427 Non-standard or SystemVerilog features for formal verification
428 ==============================================================
430 - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
431 when ``read_verilog`` is called with ``-formal``.
433 - The system task ``$initstate`` evaluates to 1 in the initial state and
436 - The system function ``$anyconst`` evaluates to any constant value. This is
437 equivalent to declaring a reg as ``rand const``, but also works outside
438 of checkers. (Yosys also supports ``rand const`` outside checkers.)
440 - The system function ``$anyseq`` evaluates to any value, possibly a different
441 value in each cycle. This is equivalent to declaring a reg as ``rand``,
442 but also works outside of checkers. (Yosys also supports ``rand``
443 variables outside checkers.)
445 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
446 formal exist-forall problems. Assumptions only hold if the trace satisfies
447 the assumption for all ``$allconst/$allseq`` values. For assertions and cover
448 statements it is sufficient if just one ``$allconst/$allseq`` value triggers
449 the property (similar to ``$anyconst/$anyseq``).
451 - Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute
452 (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
453 by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
455 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
456 supported in any clocked block.
458 - The syntax ``@($global_clock)`` can be used to create FFs that have no
459 explicit clock input ($ff cells). The same can be achieved by using
460 ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
461 is marked with the ``(* gclk *)`` Verilog attribute.
464 Supported features from SystemVerilog
465 =====================================
467 When ``read_verilog`` is called with ``-sv``, it accepts some language features
470 - The ``assert`` statement from SystemVerilog is supported in its most basic
471 form. In module context: ``assert property (<expression>);`` and within an
472 always block: ``assert(<expression>);``. It is transformed to a $assert cell.
474 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
475 also supported. The same limitations as with the ``assert`` statement apply.
477 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
478 and ``bit`` are supported.
480 - Declaring free variables with ``rand`` and ``rand const`` is supported.
482 - Checkers without a port list that do not need to be instantiated (but instead
483 behave like a named block) are supported.
485 - SystemVerilog packages are supported. Once a SystemVerilog file is read
486 into a design with ``read_verilog``, all its packages are available to
487 SystemVerilog files being read into the same design afterwards.
489 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
490 ports are inputs or outputs are supported.
493 Building the documentation
494 ==========================
496 Note that there is no need to build the manual if you just want to read it.
497 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
500 On Ubuntu, texlive needs these packages to be able to build the manual:
502 sudo apt-get install texlive-binaries
503 sudo apt-get install texlive-science # install algorithm2e.sty
504 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
505 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
506 sudo apt-get install texlive-publishers # IEEEtran.cls
508 Also the non-free font luximono should be installed, there is unfortunately
509 no Ubuntu package for this so it should be installed separately using
512 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
513 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
514 getnonfreefonts luximono # installs to /home/user/texmf
516 Then execute, from the root of the repository:
522 - To run `make manual` you need to have installed Yosys with `make install`,
523 otherwise it will fail on finding `kernel/yosys.h` while building