2 yosys -- Yosys Open SYnthesis Suite
4 Copyright (C) 2012 - 2017 Clifford Wolf <clifford@clifford.at>
6 Permission to use, copy, modify, and/or distribute this software for any
7 purpose with or without fee is hereby granted, provided that the above
8 copyright notice and this permission notice appear in all copies.
10 THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 yosys – Yosys Open SYnthesis Suite
21 ===================================
23 This is a framework for RTL synthesis tools. It currently has
24 extensive Verilog-2005 support and provides a basic set of
25 synthesis algorithms for various application domains.
27 Yosys can be adapted to perform any synthesis job by combining
28 the existing passes (algorithms) using synthesis scripts and
29 adding additional passes as needed by extending the yosys C++
32 Yosys is free software licensed under the ISC license (a GPL
33 compatible license that is similar in terms to the MIT license
34 or the 2-clause BSD license).
40 More information and documentation can be found on the Yosys web site:
41 http://www.clifford.at/yosys/
46 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
47 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
48 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
49 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
51 For example on Ubuntu Linux 16.04 LTS the following commands will install all
52 prerequisites for building yosys:
54 $ sudo apt-get install build-essential clang bison flex \
55 libreadline-dev gawk tcl-dev libffi-dev git \
56 graphviz xdot pkg-config python3
58 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
60 $ brew tap Homebrew/bundle && brew bundle
61 $ sudo port install bison flex readline gawk libffi \
62 git graphviz pkgconfig python36
64 On FreeBSD use the following command to install all prerequisites:
66 # pkg install bison flex readline gawk libffi\
67 git graphviz pkgconfig python3 python36 tcl-wrapper
69 On FreeBSD system use gmake instead of make. To run tests use:
70 % MAKE=gmake CC=cc gmake test
72 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
73 as a source distribution for Visual Studio. Visit the Yosys download page for
74 more information: http://www.clifford.at/yosys/download.html
76 To configure the build system to use a specific compiler, use one of
81 For other compilers and build configurations it might be
82 necessary to make some changes to the config section of the
85 $ vi Makefile # ..or..
88 To build Yosys simply type 'make' in this directory.
94 Note that this also downloads, builds and installs ABC (using yosys-abc
100 Yosys can be used with the interactive command shell, with
101 synthesis scripts or with command line arguments. Let's perform
102 a simple synthesis job using the interactive command shell:
107 the command ``help`` can be used to print a list of all available
108 commands and ``help <command>`` to print details on the specified command:
112 reading the design using the Verilog frontend:
114 yosys> read_verilog tests/simple/fiedler-cooley.v
116 writing the design to the console in yosys's internal format:
120 elaborate design hierarchy:
124 convert processes (``always`` blocks) to netlist elements and perform
125 some simple optimizations:
129 display design netlist using ``xdot``:
133 the same thing using ``gv`` as postscript viewer:
135 yosys> show -format ps -viewer gv
137 translating netlist to gate logic and perform some simple optimizations:
141 write design netlist to a new Verilog file:
143 yosys> write_verilog synth.v
145 a similar synthesis can be performed using yosys command line options only:
147 $ ./yosys -o synth.v -p hierarchy -p proc -p opt \
148 -p techmap -p opt tests/simple/fiedler-cooley.v
150 or using a simple synthesis script:
153 read_verilog tests/simple/fiedler-cooley.v
154 hierarchy; proc; opt; techmap; opt
155 write_verilog synth.v
159 It is also possible to only have the synthesis commands but not the read/write
160 commands in the synthesis script:
163 hierarchy; proc; opt; techmap; opt
165 $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys
167 The following very basic synthesis script should work well with all designs:
169 # check design hierarchy
172 # translate processes (always blocks)
175 # detect and optimize FSM encodings
178 # implement memories (arrays)
181 # convert to gate logic
184 If ABC is enabled in the Yosys build configuration and a cell library is given
185 in the liberty file ``mycells.lib``, the following synthesis script will
186 synthesize for the given cell library:
188 # the high-level stuff
189 hierarchy; proc; fsm; opt; memory; opt
191 # mapping to internal cell library
194 # mapping flip-flops to mycells.lib
195 dfflibmap -liberty mycells.lib
197 # mapping logic to mycells.lib
198 abc -liberty mycells.lib
203 If you do not have a liberty file but want to test this synthesis script,
204 you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources.
206 Liberty file downloads for and information about free and open ASIC standard
207 cell libraries can be found here:
209 - http://www.vlsitechnology.org/html/libraries.html
210 - http://www.vlsitechnology.org/synopsys/vsclib013.lib
212 The command ``synth`` provides a good default synthesis script (see
213 ``help synth``). If possible a synthesis script should borrow from ``synth``.
216 # the high-level stuff
220 # mapping to internal cells
222 dfflibmap -liberty mycells.lib
223 abc -liberty mycells.lib
226 Yosys is under construction. A more detailed documentation will follow.
229 Unsupported Verilog-2005 Features
230 =================================
232 The following Verilog-2005 features are not supported by
233 yosys and there are currently no plans to add support
236 - Non-synthesizable language features as defined in
237 IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002
239 - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
241 - The ``config`` keyword and library map files
243 - The ``disable``, ``primitive`` and ``specify`` statements
245 - Latched logic (is synthesized as logic with feedback loops)
248 Verilog Attributes and non-standard features
249 ============================================
251 - The ``full_case`` attribute on case statements is supported
252 (also the non-standard ``// synopsys full_case`` directive)
254 - The ``parallel_case`` attribute on case statements is supported
255 (also the non-standard ``// synopsys parallel_case`` directive)
257 - The ``// synopsys translate_off`` and ``// synopsys translate_on``
258 directives are also supported (but the use of ``` `ifdef .. `endif ```
259 is strongly recommended instead).
261 - The ``nomem2reg`` attribute on modules or arrays prohibits the
262 automatic early conversion of arrays to separate registers. This
263 is potentially dangerous. Usually the front-end has good reasons
264 for converting an array to a list of registers. Prohibiting this
265 step will likely result in incorrect synthesis results.
267 - The ``mem2reg`` attribute on modules or arrays forces the early
268 conversion of arrays to separate registers.
270 - The ``nomeminit`` attribute on modules or arrays prohibits the
271 creation of initialized memories. This effectively puts ``mem2reg``
272 on all memories that are written to in an ``initial`` block and
275 - The ``nolatches`` attribute on modules or always-blocks
276 prohibits the generation of logic-loops for latches. Instead
277 all not explicitly assigned values default to x-bits. This does
278 not affect clocked storage elements such as flip-flops.
280 - The ``nosync`` attribute on registers prohibits the generation of a
281 storage element. The register itself will always have all bits set
282 to 'x' (undefined). The variable may only be used as blocking assigned
283 temporary variable within an always block. This is mostly used internally
284 by yosys to synthesize Verilog functions and access arrays.
286 - The ``onehot`` attribute on wires mark them as onehot state register. This
287 is used for example for memory port sharing and set by the fsm_map pass.
289 - The ``blackbox`` attribute on modules is used to mark empty stub modules
290 that have the same ports as the real thing but do not contain information
291 on the internal configuration. This modules are only used by the synthesis
292 passes to identify input and output ports of cells. The Verilog backend
293 also does not output blackbox modules on default.
295 - The ``keep`` attribute on cells and wires is used to mark objects that should
296 never be removed by the optimizer. This is used for example for cells that
297 have hidden connections that are not part of the netlist, such as IO pads.
298 Setting the ``keep`` attribute on a module has the same effect as setting it
299 on all instances of the module.
301 - The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
302 command from flattening the indicated cells and modules.
304 - The ``init`` attribute on wires is set by the frontend when a register is
305 initialized "FPGA-style" with ``reg foo = val``. It can be used during
306 synthesis to add the necessary reset logic.
308 - The ``top`` attribute on a module marks this module as the top of the
309 design hierarchy. The ``hierarchy`` command sets this attribute when called
310 with ``-top``. Other commands, such as ``flatten`` and various backends
311 use this attribute to determine the top module.
313 - The ``src`` attribute is set on cells and wires created by to the string
314 ``<hdl-file-name>:<line-number>`` by the HDL front-end and is then carried
315 through the synthesis. When entities are combined, a new |-separated
316 string is created that contains all the string from the original entities.
318 - In addition to the ``(* ... *)`` attribute syntax, yosys supports
319 the non-standard ``{* ... *}`` attribute syntax to set default attributes
320 for everything that comes after the ``{* ... *}`` statement. (Reset
321 by adding an empty ``{* *}`` statement.)
323 - In module parameter and port declarations, and cell port and parameter
324 lists, a trailing comma is ignored. This simplifies writing verilog code
325 generators a bit in some cases.
327 - Modules can be declared with ``module mod_name(...);`` (with three dots
328 instead of a list of module ports). With this syntax it is sufficient
329 to simply declare a module port as 'input' or 'output' in the module
332 - When defining a macro with `define, all text between triple double quotes
333 is interpreted as macro body, even if it contains unescaped newlines. The
334 tipple double quotes are removed from the macro body. For example:
336 `define MY_MACRO(a, b) """
341 - The attribute ``via_celltype`` can be used to implement a Verilog task or
342 function by instantiating the specified cell type. The value is the name
343 of the cell type to use. For functions the name of the output port can
344 be specified by appending it to the cell type separated by a whitespace.
345 The body of the task or function is unused in this case and can be used
346 to specify a behavioral model of the cell type for simulation. For example:
348 module my_add3(A, B, C, Y);
350 input [WIDTH-1:0] A, B, C;
351 output [WIDTH-1:0] Y;
357 (* via_celltype = "my_add3 Y" *)
358 (* via_celltype_defparam_WIDTH = 32 *)
359 function [31:0] add3;
360 input [31:0] A, B, C;
368 - A limited subset of DPI-C functions is supported. The plugin mechanism
369 (see ``help plugin``) can be used to load .so files with implementations
370 of DPI-C routines. As a non-standard extension it is possible to specify
371 a plugin alias using the ``<alias>:`` syntax. For example:
374 import "DPI-C" function foo:round = real my_round (real);
375 parameter real r = my_round(12.345);
378 $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v'
380 - Sized constants (the syntax ``<size>'s?[bodh]<value>``) support constant
381 expressions as <size>. If the expression is not a simple identifier, it
382 must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010``
384 - The system tasks ``$finish`` and ``$display`` are supported in initial blocks
385 in an unconditional context (only if/case statements on parameters
386 and constant values). The intended use for this is synthesis-time DRC.
389 Non-standard or SystemVerilog features for formal verification
390 ==============================================================
392 - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
393 when ``read_verilog`` is called with ``-formal``.
395 - The system task ``$initstate`` evaluates to 1 in the initial state and
398 - The system function ``$anyconst`` evaluates to any constant value. This is
399 equivalent to declaring a reg as ``rand const``, but also works outside
400 of checkers. (Yosys also supports ``rand const`` outside checkers.)
402 - The system function ``$anyseq`` evaluates to any value, possibly a different
403 value in each cycle. This is equivalent to declaring a reg as ``rand``,
404 but also works outside of checkers. (Yosys also supports ``rand``
405 variables outside checkers.)
407 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
408 formal exist-forall problems. Assumptions only hold if the trace satisfies
409 the assumtion for all ``$allconst/$allseq`` values. For assertions and cover
410 statements it is sufficient if just one ``$allconst/$allseq`` value triggers
411 the property (similar to ``$anyconst/$anyseq``).
413 - Wires/registers decalred using the ``anyconst/anyseq/allconst/allseq`` attribute
414 (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
415 by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
417 - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are
418 supported in any clocked block.
420 - The syntax ``@($global_clock)`` can be used to create FFs that have no
421 explicit clock input ($ff cells). The same can be achieved by using
422 ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
423 is marked with the ``(* gclk *)`` Verilog attribute.
426 Supported features from SystemVerilog
427 =====================================
429 When ``read_verilog`` is called with ``-sv``, it accepts some language features
432 - The ``assert`` statement from SystemVerilog is supported in its most basic
433 form. In module context: ``assert property (<expression>);`` and within an
434 always block: ``assert(<expression>);``. It is transformed to a $assert cell.
436 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
437 also supported. The same limitations as with the ``assert`` statement apply.
439 - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic``
440 and ``bit`` are supported.
442 - Declaring free variables with ``rand`` and ``rand const`` is supported.
444 - Checkers without a port list that do not need to be instantiated (but instead
445 behave like a named block) are supported.
447 - SystemVerilog packages are supported. Once a SystemVerilog file is read
448 into a design with ``read_verilog``, all its packages are available to
449 SystemVerilog files being read into the same design afterwards.
452 Building the documentation
453 ==========================
455 Note that there is no need to build the manual if you just want to read it.
456 Simply download the PDF from http://www.clifford.at/yosys/documentation.html
459 On Ubuntu, texlive needs these packages to be able to build the manual:
461 sudo apt-get install texlive-binaries
462 sudo apt-get install texlive-science # install algorithm2e.sty
463 sudo apt-get install texlive-bibtex-extra # gets multibib.sty
464 sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty
465 sudo apt-get install texlive-publishers # IEEEtran.cls
467 Also the non-free font luximono should be installed, there is unfortunately
468 no Ubuntu package for this so it should be installed separately using
471 wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts
472 sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script
473 getnonfreefonts luximono # installs to /home/user/texmf
475 Then execute, from the root of the repository:
481 - To run `make manual` you need to have installed yosys with `make install`,
482 otherwise it will fail on finding `kernel/yosys.h` while building