RELEASE_NOTES

   1 Outstanding issues for 2.0 release:
   2 --------------------
   3 1. Fix O3 CPU bug in SE 40.perlbmk fails
   4 2. Fix O3 processing nacks/coherence messages
   5 3. Better statistics for the caches.
   6 4. FS mode doesn't work under Cygwin
   7 5. memtest regression crashes under Cygwin
   8 6. Make repository public
   9 7. Testing
  10 8. Validation
  11
  12 March 1, 2008: m5_2.0_beta5
  13 --------------------
  14 New Features
  15 1. Rick Strong's Simpoints config changes
  16 2. Support for FSU ARM port
  17 3. EXTRAS= option allow architectures to be specified
  18
  19 Bug fixes
  20 1. Bus timing more realistic
  21 2. Cache writeback, LL/SC fixes
  22 3. Minor IGbE NIC fixes
  23 4. O3 op latency fix
  24 5. SPARC TLB demap fixes
  25 6. SPARC SE memory layout fixes
  26 7. Variety of MIPS fixes
  27
  28 Nov 4, 2007: m5_2.0_beta4
  29 --------------------
  30 New Features
  31 1. New cache model
  32 2. Use of a I/O cache between devices and memory
  33 3. Ability to include compiled code with EXTRAS=
  34 4. Python creation of params structures for initialization
  35 5. Ability to remotely debug in SE
  36
  37 Bug fixes:
  38 1. Fix SE serialization
  39 2. SPARC_FS booting with TimingSimpleCPU
  40 3. Rename cycles() to ticks()
  41 4. Various SPARC ISA fixes
  42 5. Draining code for checkpointing
  43 6. Various performance improvements
  44
  45 Possible Incompatibilities:
  46 1. Real TLBs are now used in SE mode. This is more accurate however it could
  47    cause some problems if you've modified the way page handling is done in
  48    SE mode.
  49 2. There have been many changes to the way the SCons files work. SimObjects,
  50    sources files, and trace flags are all specified in the SConscript files.
  51    To see how to add your sources take a look at one of them.
  52 3. Python is now used to created the parameter structs that were created
  53    manually before. The parameters listed in a py file are turned into
  54    a header file with the same name (e.g. BadDevice.py -> BadDevice.hh).
  55    With this change the structs can be populated automatically and the
  56    ugly macros to define and create SimObjects at the bottem of source
  57    files are gone. The parameter structs also automatically inherit
  58    parameters from their parents.
  59
  60 May 16, 2007: m5_2.0_beta3
  61 --------------------
  62 New Features
  63 1. Some support for SPARC full-system simulation
  64 2. Reworking of trace facitities (parameter names changed, variadic macros
  65    removed)
  66 3. Scons script cleanups
  67 4. Some support for compiling with Intel CC
  68
  69 Bug fixes since beta 2:
  70 1. Many SPARC linux syscall emulation support fixes
  71 2. Multiprocessor linux boot using the detailed O3 CPU module
  72 3. Workaround for DMA bug (final solution to be released with 2.0f)
  73 4. Simulator performance and memory leak fixes
  74 5. Fixed issue where console could stop printing in ALPHA_FS
  75 6. Fix issues with remote debugging
  76 7. Several compile fixes, including gcc 4.1
  77 8. Many other minor fixes and enhancements
  78
  79 Nov. 28, 2006: m5_2.0_beta2
  80 --------------------
  81 Bug fixes since beta 1:
  82 1. Many cache issues resolved
  83 2. Uni-coherence fixes in full-system
  84 3. LL/SC Support
  85 4. Draining/Switchover
  86 5. Functional Accesses
  87 6. Bus now has real timing
  88 7. Single config file for all SpecCPU2000 benchmarks
  89 8. Several other minor bug fixes and enhancements
  90
  91 Aug. 25, 2006: m5_2.0_beta patch 1
  92 --------------------
  93 Handful of minor bug fixes for m5_2.0_beta,
  94 along with a few new regression tests.
  95
  96 Aug. 15, 2006: m5_2.0_beta
  97 --------------------
  98 Major update to M5 including:
  99 - New CPU model
 100 - New memory system
 101 - More extensive python integration
 102 - Preliminary syscall emulation support for MIPS and SPARC
 103 This is a *beta* release, meaning that some features are not complete,
 104 and some features from M5 1.X aren't currently supported (e.g., MP
 105 coherence).  We are working to address these limitations and hope to
 106 have a complete 2.0 release soon.
 107
 108 Oct. 8, 2005: m5_1.1
 109 --------------------
 110 Update release for IOSCA workshop mini-tutorial.  New features include:
 111 - Preliminary FreeBSD support
 112 - Integration of regression tests into scons build framework
 113 - Several bug fixes and better compatibility for Cygwin hosts
 114 - Major cleanup of Alpha system code (console, PAL, etc.) to make
 115   it easier for others to build/modify
 116 - Fixes to enable compilation under g++ 4.0
 117 - Numerous minor bug fixes
 118
 119 June 10, 2005: m5_1.0_web
 120 -------------------------
 121 The 1.0 release posted on Sourceforge after the ISCA tutorial contains
 122 just a few very minor fixes relative to the CD.
 123
 124 June 5, 2005: m5_1.0_tutorial
 125 -----------------------------
 126 First non-beta release.  This release was on the CD distributed at the
 127 ISCA tutorial.  Major enhancements relative to beta releases include
 128 Linux support and Python-based configuration language.
 129
 130 June 17, 2004: m5_1.0_beta2
 131 ---------------------------
 132 Stealth-mode beta bug-fix update, not widely advertised.
 133
 134 Oct. 17, 2003: m5_1.0_beta1
 135 ---------------------------
 136 Early beta release.