RELEASE_NOTES

   1 October 6, 2008: m5_2.0_beta6
   2 --------------------
   3 New Features
   4 1. Support for gcc 4.3
   5 2. Core m5 code in libm5 for integration with other simulators
   6 3. Preliminary support for X86 SE mode
   7 4. Additional system calls emulated
   8 5. m5term updated to work on OS X
   9 6. Ability to disable listen sockets
  10 7. Event queue performance improvements and rewrite
  11 8. Better errors for unconnected memory ports
  12
  13 Bug fixes
  14 1. ALPHA_SE O3 perlbmk benchmark
  15 2. Translation bug where O3 could fetch from uncachable memory
  16 3. Many minor bugs
  17
  18 Outstanding issues for 2.0 release:
  19 --------------------
  20 1. Statistics cleanup
  21 2. Improve regression system
  22 3. Testing
  23 4. Validation
  24
  25 March 1, 2008: m5_2.0_beta5
  26 --------------------
  27 New Features
  28 1. Rick Strong's Simpoints config changes
  29 2. Support for FSU ARM port
  30 3. EXTRAS= option allow architectures to be specified
  31
  32 Bug fixes
  33 1. Bus timing more realistic
  34 2. Cache writeback, LL/SC fixes
  35 3. Minor IGbE NIC fixes
  36 4. O3 op latency fix
  37 5. SPARC TLB demap fixes
  38 6. SPARC SE memory layout fixes
  39 7. Variety of MIPS fixes
  40
  41 Nov 4, 2007: m5_2.0_beta4
  42 --------------------
  43 New Features
  44 1. New cache model
  45 2. Use of a I/O cache between devices and memory
  46 3. Ability to include compiled code with EXTRAS=
  47 4. Python creation of params structures for initialization
  48 5. Ability to remotely debug in SE
  49
  50 Bug fixes:
  51 1. Fix SE serialization
  52 2. SPARC_FS booting with TimingSimpleCPU
  53 3. Rename cycles() to ticks()
  54 4. Various SPARC ISA fixes
  55 5. Draining code for checkpointing
  56 6. Various performance improvements
  57
  58 Possible Incompatibilities:
  59 1. Real TLBs are now used in SE mode. This is more accurate however it could
  60    cause some problems if you've modified the way page handling is done in
  61    SE mode.
  62 2. There have been many changes to the way the SCons files work. SimObjects,
  63    sources files, and trace flags are all specified in the SConscript files.
  64    To see how to add your sources take a look at one of them.
  65 3. Python is now used to created the parameter structs that were created
  66    manually before. The parameters listed in a py file are turned into
  67    a header file with the same name (e.g. BadDevice.py -> BadDevice.hh).
  68    With this change the structs can be populated automatically and the
  69    ugly macros to define and create SimObjects at the bottem of source
  70    files are gone. The parameter structs also automatically inherit
  71    parameters from their parents.
  72
  73 May 16, 2007: m5_2.0_beta3
  74 --------------------
  75 New Features
  76 1. Some support for SPARC full-system simulation
  77 2. Reworking of trace facitities (parameter names changed, variadic macros
  78    removed)
  79 3. Scons script cleanups
  80 4. Some support for compiling with Intel CC
  81
  82 Bug fixes since beta 2:
  83 1. Many SPARC linux syscall emulation support fixes
  84 2. Multiprocessor linux boot using the detailed O3 CPU module
  85 3. Workaround for DMA bug (final solution to be released with 2.0f)
  86 4. Simulator performance and memory leak fixes
  87 5. Fixed issue where console could stop printing in ALPHA_FS
  88 6. Fix issues with remote debugging
  89 7. Several compile fixes, including gcc 4.1
  90 8. Many other minor fixes and enhancements
  91
  92 Nov. 28, 2006: m5_2.0_beta2
  93 --------------------
  94 Bug fixes since beta 1:
  95 1. Many cache issues resolved
  96 2. Uni-coherence fixes in full-system
  97 3. LL/SC Support
  98 4. Draining/Switchover
  99 5. Functional Accesses
 100 6. Bus now has real timing
 101 7. Single config file for all SpecCPU2000 benchmarks
 102 8. Several other minor bug fixes and enhancements
 103
 104 Aug. 25, 2006: m5_2.0_beta patch 1
 105 --------------------
 106 Handful of minor bug fixes for m5_2.0_beta,
 107 along with a few new regression tests.
 108
 109 Aug. 15, 2006: m5_2.0_beta
 110 --------------------
 111 Major update to M5 including:
 112 - New CPU model
 113 - New memory system
 114 - More extensive python integration
 115 - Preliminary syscall emulation support for MIPS and SPARC
 116 This is a *beta* release, meaning that some features are not complete,
 117 and some features from M5 1.X aren't currently supported (e.g., MP
 118 coherence).  We are working to address these limitations and hope to
 119 have a complete 2.0 release soon.
 120
 121 Oct. 8, 2005: m5_1.1
 122 --------------------
 123 Update release for IOSCA workshop mini-tutorial.  New features include:
 124 - Preliminary FreeBSD support
 125 - Integration of regression tests into scons build framework
 126 - Several bug fixes and better compatibility for Cygwin hosts
 127 - Major cleanup of Alpha system code (console, PAL, etc.) to make
 128   it easier for others to build/modify
 129 - Fixes to enable compilation under g++ 4.0
 130 - Numerous minor bug fixes
 131
 132 June 10, 2005: m5_1.0_web
 133 -------------------------
 134 The 1.0 release posted on Sourceforge after the ISCA tutorial contains
 135 just a few very minor fixes relative to the CD.
 136
 137 June 5, 2005: m5_1.0_tutorial
 138 -----------------------------
 139 First non-beta release.  This release was on the CD distributed at the
 140 ISCA tutorial.  Major enhancements relative to beta releases include
 141 Linux support and Python-based configuration language.
 142
 143 June 17, 2004: m5_1.0_beta2
 144 ---------------------------
 145 Stealth-mode beta bug-fix update, not widely advertised.
 146
 147 Oct. 17, 2003: m5_1.0_beta1
 148 ---------------------------
 149 Early beta release.