3 The expected form of the data is:
5 * Tag (N - 79) / ASID (78 - 64) / PTE (63 - 0)
8 from nmigen
import Memory
, Module
, Signal
9 from nmigen
.cli
import main
11 from PermissionValidator
import PermissionValidator
15 def __init__(self
, asid_size
, vma_size
, pte_size
, L1_size
):
17 * asid_size: Address Space IDentifier (ASID) typically 15 bits
18 * vma_size: Virtual Memory Address (VMA) typically 36 bits
19 * pte_size: Page Table Entry (PTE) typically 64 bits
22 These arguments should represent the largest possible size
23 defined by the MODE settings. See
24 Volume II: RISC-V Privileged Architectures V1.10 Page 57
31 self
.cam_L1
= Cam(vma_size
, L1_size
)
32 self
.mem_L1
= Memory(asid_size
+ pte_size
, L1_size
)
34 # Permission Validator
35 self
.perm_validator
= PermissionValidator(asid_size
, pte_size
)
38 self
.supermode
= Signal(1) # Supervisor Mode
39 self
.super_access
= Signal(1) # Supervisor Access
40 self
.command
= Signal(2) # 00=None, 01=Search, 10=Write L1, 11=Write L2
41 self
.xwr
= Signal(3) # Execute, Write, Read
42 self
.mode
= Signal(4) # 4 bits for access to Sv48 on Rv64
43 self
.address_L1
= Signal(max=L1_size
)
44 self
.asid
= Signal(asid_size
) # Address Space IDentifier (ASID)
45 self
.vma
= Signal(vma_size
) # Virtual Memory Address (VMA)
46 self
.pte_in
= Signal(pte_size
) # To be saved Page Table Entry (PTE)
49 self
.hit
= Signal(1) # Denotes if the VMA had a mapped PTE
50 self
.perm_valid
= Signal(1) # Denotes if the permissions are correct
51 self
.pte_out
= Signal(pte_size
) # PTE that was mapped to by the VMA
53 def elaborate(self
, platform
):
56 # Submodules for L1 Cache
57 m
.d
.submodules
.cam_L1
= self
.cam_L1
58 m
.d
.sumbmodules
.read_L1
= read_L1
= self
.mem_L1
.read_port
59 m
.d
.sumbmodules
.read_L1
= write_L1
= self
.mem_L1
.read_port
60 # Permission Validator Submodule
61 m
.d
.submodules
.perm_valididator
= self
.perm_validator
63 # When MODE specifies translation
64 # TODO add in different bit length handling ie prefix 0s
65 with m
.If(self
.mode
!= 0):
67 self
.cam_L1
.enable
.eq(1)
69 with m
.Switch(self
.command
):
74 self
.cam_L1
.write_enable
.eq(0),
75 self
.cam_L1
.data_in
.eq(self
.vma
)
78 # Expected that the miss will be handled in software
83 write_L1
.addr
.eq(self
.address_L1
),
84 # The first argument is the LSB
85 write_L1
.data
.eq(Cat(self
.pte
, self
.asid
))
89 self
.cam_L1
.write_enable
.eq(1),
90 self
.cam_L1
.data_in
.eq(self
.vma
),
95 # Match found in L1 CAM
96 with m
.If(self
.cam_L1
.single_match
97 | self
.cam_L1
.multiple_match
):
98 # Memory shortcut variables
99 mem_addrress
= self
.cam_L1
.match_address
101 m
.d
.comb
+= read_L1
.addr(mem_address
)
102 # Permission Validator Logic
105 # Set permission validator data to the correct
106 # register file data according to CAM match
108 self
.perm_validator
.data
.eq(read_L1
.data
),
109 # Execute, Read, Write
110 self
.perm_validator
.xwr
.eq(self
.xwr
),
112 self
.perm_validator
.supermode
.eq(self
.supermode
),
114 self
.perm_validator
.super_access
.eq(self
.super_access
),
115 # Address Space IDentifier (ASID)
116 self
.perm_validator
.asid
.eq(self
.asid
),
117 # Output result of permission validation
118 self
.perm_valid
.eq(self
.perm_validator
.valid
)
120 # Do not output PTE if permissions fail
121 with m
.If(self
.perm_validator
.valid
):
123 self
.pte_out
.eq(reg_data
)
133 self
.perm_valid
.eq(0),
139 self
.cam_L1
.enable
.eq(0),
140 self
.reg_file
.enable
.eq(0),