2 sys
.path
.append("../src")
3 sys
.path
.append("../../TestUtil")
5 from nmigen
.compat
.sim
import run_simulation
9 from test_helper
import assert_eq
, assert_ne
, assert_op
11 # This function allows for the easy setting of values to the Cam
13 # dut: The Cam being tested
14 # e (Enable): Whether the block is going to be enabled
15 # we (Write Enable): Whether the Cam will write on the next cycle
16 # a (Address): Where the data will be written if write enable is high
17 # d (Data): Either what we are looking for or will write to the address
18 def set_cam(dut
, e
, we
, a
, d
):
19 yield dut
.enable
.eq(e
)
20 yield dut
.write_enable
.eq(we
)
21 yield dut
.address_in
.eq(a
)
22 yield dut
.data_in
.eq(d
)
25 # Checks the multiple match of the Cam
27 # dut: The Cam being tested
28 # mm (Multiple Match): The expected match result
29 # op (Operation): (0 => ==), (1 => !=)
30 def check_multiple_match(dut
, mm
, op
):
31 out_mm
= yield dut
.multiple_match
32 assert_op("Multiple Match", out_mm
, mm
, op
)
34 # Checks the single match of the Cam
36 # dut: The Cam being tested
37 # sm (Single Match): The expected match result
38 # op (Operation): (0 => ==), (1 => !=)
39 def check_single_match(dut
, sm
, op
):
40 out_sm
= yield dut
.single_match
41 assert_op("Single Match", out_sm
, sm
, op
)
43 # Checks the address output of the Cam
45 # dut: The Cam being tested
46 # ma (Match Address): The expected match result
47 # op (Operation): (0 => ==), (1 => !=)
48 def check_match_address(dut
, ma
, op
):
49 out_ma
= yield dut
.match_address
50 assert_op("Match Address", out_ma
, ma
, op
)
52 # Checks the state of the Cam
54 # dut: The Cam being tested
55 # sm (Single Match): The expected match result
56 # mm (Multiple Match): The expected match result
57 # ma: (Match Address): The expected address output
58 # ss_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
59 # mm_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
60 # ma_op (Operation): Operation for the address assertion (0 => ==), (1 => !=)
61 def check_all(dut
, mm
, sm
, ma
, mm_op
, sm_op
, ma_op
):
62 yield from check_multiple_match(dut
, mm
, mm_op
)
63 yield from check_single_match(dut
, sm
, sm_op
)
64 yield from check_match_address(dut
, ma
, ma_op
)
73 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
75 yield from check_single_match(dut
, single_match
, 0)
78 # Note that the default starting entry data bits are all 0
85 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
87 yield from check_multiple_match(dut
, multiple_match
, 0)
90 # Note that the default starting entry data bits are all 0
97 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
99 yield from check_single_match(dut
, single_match
, 0)
108 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
110 yield from check_single_match(dut
, single_match
, 0)
119 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
121 yield from check_all(dut
, multiple_match
, single_match
, address
, 0, 0, 0)
130 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
132 yield from check_all(dut
, multiple_match
, single_match
, address
, 0, 0, 0)
140 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
142 yield from check_single_match(dut
, single_match
, 0)
144 # Multiple Match test
152 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
154 yield from check_single_match(dut
, single_match
, 0)
157 # Same data as Entry 1
164 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
166 yield from check_single_match(dut
, single_match
, 0)
175 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
177 yield from check_all(dut
, multiple_match
, single_match
, address
,0,0,0)
179 # Verify read_warning is not caused
187 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
188 # Note there is no yield we immediately attempt to read in the next cycle
197 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
199 yield from check_single_match(dut
, single_match
, 0)
204 if __name__
== "__main__":
206 run_simulation(dut
, testbench(dut
), vcd_name
="Waveforms/test_cam.vcd")
207 print("Cam Unit Test Success")