2 sys
.path
.append("../src")
3 sys
.path
.append("../../TestUtil")
5 from nmigen
.compat
.sim
import run_simulation
9 from test_helper
import assert_eq
, assert_ne
11 def set_cam(dut
, e
, we
, a
, d
):
12 yield dut
.enable
.eq(e
)
13 yield dut
.write_enable
.eq(we
)
14 yield dut
.address_in
.eq(a
)
15 yield dut
.data_in
.eq(d
)
18 def check_single_match(dut
, dh
, op
):
19 out_sm
= yield dut
.single_match
21 assert_eq("Single Match", out_sm
, dh
)
23 assert_ne("Single Match", out_sm
, dh
)
25 def check_match_address(dut
, ma
, op
):
26 out_ma
= yield dut
.match_address
28 assert_eq("Match Address", out_ma
, ma
)
30 assert_ne("Match Address", out_ma
, ma
)
32 def check_all(dut
, single_match
, match_address
, sm_op
, ma_op
):
33 yield from check_single_match(dut
, single_match
, sm_op
)
34 yield from check_match_address(dut
, match_address
, ma_op
)
44 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
45 yield from check_single_match(dut
, single_match
, 0)
48 # Note that the default starting entry data bits are all 0
54 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
56 yield from check_single_match(dut
, single_match
, 0)
64 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
66 yield from check_single_match(dut
, single_match
, 0)
74 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
76 yield from check_all(dut
, single_match
, address
, 0, 0)
84 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
86 yield from check_all(dut
, single_match
, address
, 0, 0)
94 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
96 yield from check_single_match(dut
, single_match
, 0)
101 if __name__
== "__main__":
103 run_simulation(dut
, testbench(dut
), vcd_name
="Waveforms/cam_test.vcd")
104 print("Cam Unit Test Success")