2 sys
.path
.append("../src")
3 sys
.path
.append("../../TestUtil")
5 from nmigen
.compat
.sim
import run_simulation
7 from RegisterFile
import RegisterFile
9 from test_helper
import assert_eq
, assert_ne
, assert_op
11 def setRegisterFile(dut
, e
, we
, a
, di
):
12 yield dut
.enable
.eq(e
)
13 yield dut
.write_enable
.eq(we
)
14 yield dut
.address
.eq(a
)
15 yield dut
.data_i
.eq(di
)
18 # Checks the address output of the Cam
20 # dut: The Cam being tested
21 # v (Valid): If the output is valid or not
22 # op (Operation): (0 => ==), (1 => !=)
23 def check_valid(dut
, v
, op
):
24 out_v
= yield dut
.valid
25 assert_op("Valid", out_v
, v
, op
)
27 # Checks the address output of the Cam
29 # dut: The Cam being tested
30 # do (Data Out): The current output data
31 # op (Operation): (0 => ==), (1 => !=)
32 def check_data(dut
, do
, op
):
33 out_do
= yield dut
.data_o
34 assert_op("Data Out", out_do
, do
, op
)
36 # Checks the address output of the Cam
38 # dut: The Cam being tested
39 # v (Valid): If the output is valid or not
40 # do (Data Out): The current output data
41 # v_op (Operation): Operation for the valid assertion (0 => ==), (1 => !=)
42 # do_op (Operation): Operation for the data assertion (0 => ==), (1 => !=)
43 def check_all(dut
, v
, do
, v_op
, do_op
):
44 yield from check_valid(dut
, v
, v_op
)
45 yield from check_data(dut
, do
, do_op
)
54 yield from setRegisterFile(dut
, enable
, write_enable
, address
, data
)
56 yield from check_all(dut
, valid
, 0, 0, 0)
64 yield from setRegisterFile(dut
, enable
, write_enable
, address
, data
)
66 yield from check_all(dut
, valid
, data
, 0, 0)
74 yield from setRegisterFile(dut
, enable
, write_enable
, address
, data
)
76 yield from check_all(dut
, valid
, 0, 0, 0)
84 yield from setRegisterFile(dut
, enable
, write_enable
, address
, data
)
86 yield from check_all(dut
, valid
, data
, 0, 0)
94 yield from setRegisterFile(dut
, enable
, write_enable
, address
, data
)
96 yield from check_all(dut
, valid
, data
, 0, 0)
104 yield from setRegisterFile(dut
, enable
, write_enable
, address
, data
)
106 yield from check_all(dut
, valid
, 0, 0, 0)
114 yield from setRegisterFile(dut
, enable
, write_enable
, address
, data
)
116 yield from check_all(dut
, valid
, data
, 0, 0)
118 if __name__
== "__main__":
119 dut
= RegisterFile(4, 4)
120 run_simulation(dut
, testbench(dut
), vcd_name
="Waveforms/test_register_file.vcd")
121 print("RegisterFile Unit Test Success")