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  18 Date: Fri, 08 May 2020 17:27:06 +0200
  19 From: whygee@f-cpu.org
  20 To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
  21 In-Reply-To: <CAPweEDw862-S1=Au1YbsKNy0629pa56eShp+2o_Avd96Auz8mw@mail.gmail.com>
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  26 Subject: [libre-riscv-dev] Debug port (was Re:  minimum viable ASIC)
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