aquila/third_party/async_fifo/async_fifo.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright 2017 Damien Pretet ThotIP
   3 //
   4 // Licensed under the Apache License, Version 2.0 (the "License");
   5 // you may not use this file except in compliance with the License.
   6 // You may obtain a copy of the License at
   7 //
   8 //     http://www.apache.org/licenses/LICENSE-2.0
   9 //
  10 // Unless required by applicable law or agreed to in writing, software
  11 // distributed under the License is distributed on an "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13 // See the License for the specific language governing permissions and
  14 // limitations under the License.
  15 //-----------------------------------------------------------------------------
  16
  17 `timescale 1 ns / 1 ps
  18 `default_nettype none
  19
  20 module async_fifo
  21
  22     #(
  23     parameter DSIZE = 8,
  24     parameter ASIZE = 4,
  25     parameter FALLTHROUGH = "TRUE" // First word fall-through
  26     )(
  27     input  wire             wclk,
  28     input  wire             wrst_n,
  29     input  wire             winc,
  30     input  wire [DSIZE-1:0] wdata,
  31     output wire             wfull,
  32     output wire             awfull,
  33     input  wire             rclk,
  34     input  wire             rrst_n,
  35     input  wire             rinc,
  36     output wire [DSIZE-1:0] rdata,
  37     output wire             rempty,
  38     output wire             arempty,
  39     output wire [ASIZE  :0] rclk_rptr,
  40     output wire [ASIZE  :0] rclk_wptr,
  41     output wire [ASIZE  :0] wclk_rptr,
  42     output wire [ASIZE  :0] wclk_wptr
  43     );
  44
  45     wire [  ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
  46     wire [ASIZE-1:0] wclk_wptr_internal, rclk_rptr_internal;
  47
  48     assign wclk_wptr = {1'b0, wclk_wptr_internal};
  49     assign rclk_rptr = {1'b0, rclk_rptr_internal};
  50
  51     // The module synchronizing the read point
  52     // from read to write domain
  53     sync_r2w
  54     #(ASIZE)
  55     sync_r2w (
  56     .wq2_rptr (wq2_rptr),
  57     .rptr     (rptr),
  58     .wclk     (wclk),
  59     .wrst_n   (wrst_n)
  60     );
  61
  62     // The module synchronizing the write point
  63     // from write to read domain
  64     sync_w2r
  65     #(ASIZE)
  66     sync_w2r (
  67     .rq2_wptr (rq2_wptr),
  68     .wptr     (wptr),
  69     .rclk     (rclk),
  70     .rrst_n   (rrst_n)
  71     );
  72
  73     // The module handling the write requests
  74     wptr_full
  75     #(ASIZE)
  76     wptr_full (
  77     .awfull   (awfull),
  78     .wfull    (wfull),
  79     .waddr    (wclk_wptr_internal),
  80     .wptr     (wptr),
  81     .wq2_rptr (wq2_rptr),
  82     .winc     (winc),
  83     .wclk     (wclk),
  84     .wrst_n   (wrst_n),
  85     .wq2_rptr_binary (wclk_rptr)
  86     );
  87
  88     // The DC-RAM
  89     fifomem
  90     #(DSIZE, ASIZE, FALLTHROUGH)
  91     fifomem (
  92     .rclken (rinc),
  93     .rclk   (rclk),
  94     .rdata  (rdata),
  95     .wdata  (wdata),
  96     .waddr  (wclk_wptr_internal),
  97     .raddr  (rclk_rptr_internal),
  98     .wclken (winc),
  99     .wfull  (wfull),
 100     .wclk   (wclk)
 101     );
 102
 103     // The module handling read requests
 104     rptr_empty
 105     #(ASIZE)
 106     rptr_empty (
 107     .arempty  (arempty),
 108     .rempty   (rempty),
 109     .raddr    (rclk_rptr_internal),
 110     .rptr     (rptr),
 111     .rq2_wptr (rq2_wptr),
 112     .rinc     (rinc),
 113     .rclk     (rclk),
 114     .rrst_n   (rrst_n),
 115     .rq2_wptr_binary (rclk_wptr)
 116     );
 117
 118 endmodule
 119
 120 `resetall