aquila/third_party/async_fifo/fifomem_dp.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright 2017 Damien Pretet ThotIP
   3 // Copyright 2018 Julius Baxter
   4 //
   5 // Licensed under the Apache License, Version 2.0 (the "License");
   6 // you may not use this file except in compliance with the License.
   7 // You may obtain a copy of the License at
   8 //
   9 //     http://www.apache.org/licenses/LICENSE-2.0
  10 //
  11 // Unless required by applicable law or agreed to in writing, software
  12 // distributed under the License is distributed on an "AS IS" BASIS,
  13 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14 // See the License for the specific language governing permissions and
  15 // limitations under the License.
  16 //-----------------------------------------------------------------------------
  17
  18 `timescale 1 ns / 1 ps
  19 `default_nettype none
  20
  21 module fifomem_dp
  22
  23     #(
  24     parameter  DATASIZE     = 8,      // Memory data word width
  25     parameter  ADDRSIZE     = 4,      // Number of mem address bits
  26     parameter  FALLTHROUGH  = "TRUE"  // First word fall-through
  27     ) (
  28     input wire                a_clk,
  29     input wire [DATASIZE-1:0] a_wdata,
  30     output reg [DATASIZE-1:0] a_rdata,
  31     input wire [ADDRSIZE-1:0] a_addr,
  32     input wire                a_rinc,
  33     input wire                a_winc,
  34
  35     input wire                b_clk,
  36     input wire [DATASIZE-1:0] b_wdata,
  37     output reg [DATASIZE-1:0] b_rdata,
  38     input wire [ADDRSIZE-1:0] b_addr,
  39     input wire                b_rinc,
  40     input wire                b_winc
  41     );
  42
  43 generate
  44   begin : dpram
  45
  46     localparam DEPTH = 1<<ADDRSIZE;
  47     reg [DATASIZE-1:0] mem [0:DEPTH-1];
  48
  49   if (FALLTHROUGH == "TRUE")
  50     begin : fallthrough
  51
  52       always @(posedge a_clk)
  53         if (a_winc)
  54           mem[a_addr] <= a_wdata;
  55
  56       always @*
  57         a_rdata  = mem[a_addr];
  58
  59       always @(posedge b_clk)
  60         if (b_winc)
  61           mem[b_addr] <= b_wdata;
  62
  63       always @*
  64         b_rdata  = mem[b_addr];
  65
  66     end // block: fallthrough
  67   else
  68     begin : registered
  69
  70       wire a_en = a_rinc | a_winc;
  71
  72       always @(posedge a_clk)
  73         if (a_en)
  74           begin
  75             if (a_winc)
  76               mem[a_addr] <= a_wdata;
  77             a_rdata <= mem[a_addr];
  78           end
  79
  80       wire b_en = b_rinc | b_winc;
  81
  82       always @(posedge b_clk)
  83         if (b_en)
  84           begin
  85             if (b_winc)
  86               mem[b_addr] <= b_wdata;
  87             b_rdata <= mem[b_addr];
  88           end
  89     end // block: registered
  90   end // block: dpram
  91 endgenerate
  92
  93
  94 endmodule
  95
  96 `resetall