2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "base/inifile.hh"
34 #include "base/str.hh"
35 #include "base/trace.hh"
36 #include "cpu/exec_context.hh"
37 #include "sim/builder.hh"
38 #include "targetarch/alpha_memory.hh"
39 #include "targetarch/ev5.hh"
43 ///////////////////////////////////////////////////////////////////////
47 AlphaTlb::AlphaTlb(const string
&name
, int s
)
48 : SimObject(name
), size(s
), nlu(0)
50 table
= new AlphaISA::PTE
[size
];
51 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
60 // look up an entry in the TLB
62 AlphaTlb::lookup(Addr vpn
, uint8_t asn
) const
64 DPRINTF(TLB
, "lookup %#x\n", vpn
);
66 PageTable::const_iterator i
= lookupTable
.find(vpn
);
67 if (i
== lookupTable
.end())
70 while (i
->first
== vpn
) {
71 int index
= i
->second
;
72 AlphaISA::PTE
*pte
= &table
[index
];
74 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
))
86 AlphaTlb::checkCacheability(MemReqPtr
&req
)
88 // in Alpha, cacheability is controlled by upper-level bits of the
90 if (req
->paddr
& PA_UNCACHED_BIT
) {
91 if (PA_IPR_SPACE(req
->paddr
)) {
92 // IPR memory space not implemented
93 if (!req
->xc
->misspeculating()) {
100 panic("IPR memory space not implemented! PA=%x\n",
105 // mark request as uncacheable
106 req
->flags
|= UNCACHEABLE
;
112 // insert a new TLB entry
114 AlphaTlb::insert(Addr vaddr
, AlphaISA::PTE
&pte
)
116 if (table
[nlu
].valid
) {
117 Addr oldvpn
= table
[nlu
].tag
;
118 PageTable::iterator i
= lookupTable
.find(oldvpn
);
120 if (i
== lookupTable
.end())
121 panic("TLB entry not found in lookupTable");
124 while ((index
= i
->second
) != nlu
) {
125 if (table
[index
].tag
!= oldvpn
)
126 panic("TLB entry not found in lookupTable");
131 DPRINTF(TLB
, "remove @%d: %#x -> %#x\n", nlu
, oldvpn
, table
[nlu
].ppn
);
133 lookupTable
.erase(i
);
136 Addr vpn
= VA_VPN(vaddr
);
137 DPRINTF(TLB
, "insert @%d: %#x -> %#x\n", nlu
, vpn
, pte
.ppn
);
140 table
[nlu
].tag
= vpn
;
141 table
[nlu
].valid
= true;
143 lookupTable
.insert(make_pair(vpn
, nlu
));
150 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
156 AlphaTlb::flushProcesses()
158 PageTable::iterator i
= lookupTable
.begin();
159 PageTable::iterator end
= lookupTable
.end();
161 int index
= i
->second
;
162 AlphaISA::PTE
*pte
= &table
[index
];
166 DPRINTF(TLB
, "flush @%d: %#x -> %#x\n", index
, pte
->tag
, pte
->ppn
);
168 lookupTable
.erase(i
);
176 AlphaTlb::flushAddr(Addr vaddr
, uint8_t asn
)
178 Addr vpn
= VA_VPN(vaddr
);
180 PageTable::iterator i
= lookupTable
.find(vpn
);
181 if (i
== lookupTable
.end())
184 while (i
->first
== vpn
) {
185 int index
= i
->second
;
186 AlphaISA::PTE
*pte
= &table
[index
];
189 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
)) {
190 DPRINTF(TLB
, "flushaddr @%d: %#x -> %#x\n", index
, vpn
, pte
->ppn
);
192 // invalidate this entry
195 lookupTable
.erase(i
);
204 AlphaTlb::serialize(ostream
&os
)
206 SERIALIZE_SCALAR(size
);
207 SERIALIZE_SCALAR(nlu
);
209 for (int i
= 0; i
< size
; i
++) {
210 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
211 table
[i
].serialize(os
);
216 AlphaTlb::unserialize(Checkpoint
*cp
, const string
§ion
)
218 UNSERIALIZE_SCALAR(size
);
219 UNSERIALIZE_SCALAR(nlu
);
221 for (int i
= 0; i
< size
; i
++) {
222 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
223 if (table
[i
].valid
) {
224 lookupTable
.insert(make_pair(table
[i
].tag
, i
));
230 ///////////////////////////////////////////////////////////////////////
234 AlphaItb::AlphaItb(const std::string
&name
, int size
)
235 : AlphaTlb(name
, size
)
243 .name(name() + ".hits")
246 .name(name() + ".misses")
249 .name(name() + ".acv")
252 .name(name() + ".accesses")
253 .desc("ITB accesses");
255 accesses
= hits
+ misses
;
259 AlphaItb::fault(Addr pc
, ExecContext
*xc
) const
261 uint64_t *ipr
= xc
->regs
.ipr
;
263 if (!xc
->misspeculating()) {
264 ipr
[AlphaISA::IPR_ITB_TAG
] = pc
;
265 ipr
[AlphaISA::IPR_IFAULT_VA_FORM
] =
266 ipr
[AlphaISA::IPR_IVPTBR
] | (VA_VPN(pc
) << 3);
272 AlphaItb::translate(MemReqPtr
&req
) const
274 InternalProcReg
*ipr
= req
->xc
->regs
.ipr
;
276 if (PC_PAL(req
->vaddr
)) {
277 // strip off PAL PC marker (lsb is 1)
278 req
->paddr
= (req
->vaddr
& ~3) & PA_IMPL_MASK
;
283 // verify that this is a good virtual address
284 if (!validVirtualAddress(req
->vaddr
)) {
285 fault(req
->vaddr
, req
->xc
);
287 return Itb_Acv_Fault
;
290 // Check for "superpage" mapping: when SP<1> is set, and
291 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
292 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) &&
293 VA_SPACE(req
->vaddr
) == 2) {
294 // only valid in kernel mode
295 if (ICM_CM(ipr
[AlphaISA::IPR_ICM
]) != AlphaISA::mode_kernel
) {
296 fault(req
->vaddr
, req
->xc
);
298 return Itb_Acv_Fault
;
301 req
->flags
|= PHYSICAL
;
304 if (req
->flags
& PHYSICAL
) {
305 req
->paddr
= req
->vaddr
& PA_IMPL_MASK
;
307 // not a physical address: need to look up pte
309 AlphaISA::PTE
*pte
= lookup(VA_VPN(req
->vaddr
),
310 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
313 fault(req
->vaddr
, req
->xc
);
315 return Itb_Fault_Fault
;
318 req
->paddr
= PA_PFN2PA(pte
->ppn
) + VA_POFS(req
->vaddr
& ~3);
320 // check permissions for this access
321 if (!(pte
->xre
& (1 << ICM_CM(ipr
[AlphaISA::IPR_ICM
])))) {
322 // instruction access fault
323 fault(req
->vaddr
, req
->xc
);
325 return Itb_Acv_Fault
;
329 checkCacheability(req
);
335 ///////////////////////////////////////////////////////////////////////
339 AlphaDtb::AlphaDtb(const std::string
&name
, int size
)
340 : AlphaTlb(name
, size
)
347 .name(name() + ".read_hits")
348 .desc("DTB read hits")
352 .name(name() + ".read_misses")
353 .desc("DTB read misses")
357 .name(name() + ".read_acv")
358 .desc("DTB read access violations")
362 .name(name() + ".read_accesses")
363 .desc("DTB read accesses")
367 .name(name() + ".write_hits")
368 .desc("DTB write hits")
372 .name(name() + ".write_misses")
373 .desc("DTB write misses")
377 .name(name() + ".write_acv")
378 .desc("DTB write access violations")
382 .name(name() + ".write_accesses")
383 .desc("DTB write accesses")
387 .name(name() + ".hits")
392 .name(name() + ".misses")
397 .name(name() + ".acv")
398 .desc("DTB access violations")
402 .name(name() + ".accesses")
403 .desc("DTB accesses")
406 hits
= read_hits
+ write_hits
;
407 misses
= read_misses
+ write_misses
;
408 acv
= read_acv
+ write_acv
;
409 accesses
= read_accesses
+ write_accesses
;
413 AlphaDtb::fault(Addr vaddr
, uint64_t flags
, ExecContext
*xc
) const
415 uint64_t *ipr
= xc
->regs
.ipr
;
417 // set fault address and flags
418 if (!xc
->misspeculating() && !xc
->regs
.intrlock
) {
419 // set VA register with faulting address
420 ipr
[AlphaISA::IPR_VA
] = vaddr
;
422 // set MM_STAT register flags
423 ipr
[AlphaISA::IPR_MM_STAT
] = (((xc
->regs
.opcode
& 0x3f) << 11)
424 | ((xc
->regs
.ra
& 0x1f) << 6)
427 // set VA_FORM register with faulting formatted address
428 ipr
[AlphaISA::IPR_VA_FORM
] =
429 ipr
[AlphaISA::IPR_MVPTBR
] | (VA_VPN(vaddr
) << 3);
431 // lock these registers until the VA register is read
432 xc
->regs
.intrlock
= true;
437 AlphaDtb::translate(MemReqPtr
&req
, bool write
) const
439 RegFile
*regs
= &req
->xc
->regs
;
441 InternalProcReg
*ipr
= regs
->ipr
;
448 AlphaISA::mode_type mode
=
449 (AlphaISA::mode_type
)DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]);
452 mode
= (req
->flags
& ALTMODE
) ?
453 (AlphaISA::mode_type
)ALT_MODE_AM(ipr
[AlphaISA::IPR_ALT_MODE
])
454 : AlphaISA::mode_kernel
;
457 // verify that this is a good virtual address
458 if (!validVirtualAddress(req
->vaddr
)) {
460 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_BAD_VA_MASK
|
464 if (write
) { write_acv
++; } else { read_acv
++; }
465 return Dtb_Fault_Fault
;
468 // Check for "superpage" mapping: when SP<1> is set, and
469 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
470 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) && VA_SPACE(req
->vaddr
) == 2) {
471 // only valid in kernel mode
472 if (DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]) != AlphaISA::mode_kernel
) {
474 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_ACV_MASK
),
476 if (write
) { write_acv
++; } else { read_acv
++; }
477 return Dtb_Acv_Fault
;
480 req
->flags
|= PHYSICAL
;
483 if (req
->flags
& PHYSICAL
) {
484 req
->paddr
= req
->vaddr
& PA_IMPL_MASK
;
486 // not a physical address: need to look up pte
488 AlphaISA::PTE
*pte
= lookup(VA_VPN(req
->vaddr
),
489 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
494 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_DTB_MISS_MASK
),
496 if (write
) { write_misses
++; } else { read_misses
++; }
497 return (req
->flags
& VPTE
) ? Pdtb_Miss_Fault
: Ndtb_Miss_Fault
;
500 req
->paddr
= PA_PFN2PA(pte
->ppn
) | VA_POFS(req
->vaddr
);
503 if (!(pte
->xwe
& MODE2MASK(mode
))) {
504 // declare the instruction access fault
505 fault(req
->vaddr
, MM_STAT_WR_MASK
| MM_STAT_ACV_MASK
|
506 (pte
->fonw
? MM_STAT_FONW_MASK
: 0),
509 return Dtb_Fault_Fault
;
512 fault(req
->vaddr
, MM_STAT_WR_MASK
| MM_STAT_FONW_MASK
,
515 return Dtb_Fault_Fault
;
518 if (!(pte
->xre
& MODE2MASK(mode
))) {
520 MM_STAT_ACV_MASK
| (pte
->fonr
? MM_STAT_FONR_MASK
: 0),
523 return Dtb_Acv_Fault
;
526 fault(req
->vaddr
, MM_STAT_FONR_MASK
, req
->xc
);
528 return Dtb_Fault_Fault
;
533 checkCacheability(req
);
546 AlphaISA::PTE
*pte
= &table
[nlu
];
552 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaItb
)
556 END_DECLARE_SIM_OBJECT_PARAMS(AlphaItb
)
558 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaItb
)
560 INIT_PARAM_DFLT(size
, "TLB size", 48)
562 END_INIT_SIM_OBJECT_PARAMS(AlphaItb
)
565 CREATE_SIM_OBJECT(AlphaItb
)
567 return new AlphaItb(getInstanceName(), size
);
570 REGISTER_SIM_OBJECT("AlphaITB", AlphaItb
)
572 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb
)
576 END_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb
)
578 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDtb
)
580 INIT_PARAM_DFLT(size
, "TLB size", 64)
582 END_INIT_SIM_OBJECT_PARAMS(AlphaDtb
)
585 CREATE_SIM_OBJECT(AlphaDtb
)
587 return new AlphaDtb(getInstanceName(), size
);
590 REGISTER_SIM_OBJECT("AlphaDTB", AlphaDtb
)