2 * Copyright (c) 2001-2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 #include "base/inifile.hh"
34 #include "base/str.hh"
35 #include "base/trace.hh"
36 #include "cpu/exec_context.hh"
37 #include "sim/builder.hh"
38 #include "targetarch/alpha_memory.hh"
39 #include "targetarch/ev5.hh"
43 ///////////////////////////////////////////////////////////////////////
48 bool uncacheBit39
= false;
49 bool uncacheBit40
= false;
52 AlphaTLB::AlphaTLB(const string
&name
, int s
)
53 : SimObject(name
), size(s
), nlu(0)
55 table
= new AlphaISA::PTE
[size
];
56 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
65 // look up an entry in the TLB
67 AlphaTLB::lookup(Addr vpn
, uint8_t asn
) const
69 DPRINTF(TLB
, "lookup %#x\n", vpn
);
71 PageTable::const_iterator i
= lookupTable
.find(vpn
);
72 if (i
== lookupTable
.end())
75 while (i
->first
== vpn
) {
76 int index
= i
->second
;
77 AlphaISA::PTE
*pte
= &table
[index
];
79 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
))
91 AlphaTLB::checkCacheability(MemReqPtr
&req
)
93 // in Alpha, cacheability is controlled by upper-level bits of the
97 * We support having the uncacheable bit in either bit 39 or bit 40.
98 * The Turbolaser platform (and EV5) support having the bit in 39, but
99 * Tsunami (which Linux assumes uses an EV6) generates accesses with
100 * the bit in 40. So we must check for both, but we have debug flags
101 * to catch a weird case where both are used, which shouldn't happen.
104 if (req
->paddr
& PA_UNCACHED_BIT_43
) {
105 // IPR memory space not implemented
106 if (PA_IPR_SPACE(req
->paddr
))
107 if (!req
->xc
->misspeculating())
108 panic("IPR memory space not implemented! PA=%x\n",
111 // mark request as uncacheable
112 req
->flags
|= UNCACHEABLE
;
114 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
115 req
->paddr
&= PA_UNCACHED_MASK
;
120 // insert a new TLB entry
122 AlphaTLB::insert(Addr vaddr
, AlphaISA::PTE
&pte
)
124 if (table
[nlu
].valid
) {
125 Addr oldvpn
= table
[nlu
].tag
;
126 PageTable::iterator i
= lookupTable
.find(oldvpn
);
128 if (i
== lookupTable
.end())
129 panic("TLB entry not found in lookupTable");
132 while ((index
= i
->second
) != nlu
) {
133 if (table
[index
].tag
!= oldvpn
)
134 panic("TLB entry not found in lookupTable");
139 DPRINTF(TLB
, "remove @%d: %#x -> %#x\n", nlu
, oldvpn
, table
[nlu
].ppn
);
141 lookupTable
.erase(i
);
144 Addr vpn
= VA_VPN(vaddr
);
145 DPRINTF(TLB
, "insert @%d: %#x -> %#x\n", nlu
, vpn
, pte
.ppn
);
148 table
[nlu
].tag
= vpn
;
149 table
[nlu
].valid
= true;
151 lookupTable
.insert(make_pair(vpn
, nlu
));
158 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
164 AlphaTLB::flushProcesses()
166 PageTable::iterator i
= lookupTable
.begin();
167 PageTable::iterator end
= lookupTable
.end();
169 int index
= i
->second
;
170 AlphaISA::PTE
*pte
= &table
[index
];
174 DPRINTF(TLB
, "flush @%d: %#x -> %#x\n", index
, pte
->tag
, pte
->ppn
);
176 lookupTable
.erase(i
);
184 AlphaTLB::flushAddr(Addr vaddr
, uint8_t asn
)
186 Addr vpn
= VA_VPN(vaddr
);
188 PageTable::iterator i
= lookupTable
.find(vpn
);
189 if (i
== lookupTable
.end())
192 while (i
->first
== vpn
) {
193 int index
= i
->second
;
194 AlphaISA::PTE
*pte
= &table
[index
];
197 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
)) {
198 DPRINTF(TLB
, "flushaddr @%d: %#x -> %#x\n", index
, vpn
, pte
->ppn
);
200 // invalidate this entry
203 lookupTable
.erase(i
);
212 AlphaTLB::serialize(ostream
&os
)
214 SERIALIZE_SCALAR(size
);
215 SERIALIZE_SCALAR(nlu
);
217 for (int i
= 0; i
< size
; i
++) {
218 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
219 table
[i
].serialize(os
);
224 AlphaTLB::unserialize(Checkpoint
*cp
, const string
§ion
)
226 UNSERIALIZE_SCALAR(size
);
227 UNSERIALIZE_SCALAR(nlu
);
229 for (int i
= 0; i
< size
; i
++) {
230 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
231 if (table
[i
].valid
) {
232 lookupTable
.insert(make_pair(table
[i
].tag
, i
));
238 ///////////////////////////////////////////////////////////////////////
242 AlphaITB::AlphaITB(const std::string
&name
, int size
)
243 : AlphaTLB(name
, size
)
251 .name(name() + ".hits")
254 .name(name() + ".misses")
257 .name(name() + ".acv")
260 .name(name() + ".accesses")
261 .desc("ITB accesses");
263 accesses
= hits
+ misses
;
267 AlphaITB::fault(Addr pc
, ExecContext
*xc
) const
269 uint64_t *ipr
= xc
->regs
.ipr
;
271 if (!xc
->misspeculating()) {
272 ipr
[AlphaISA::IPR_ITB_TAG
] = pc
;
273 ipr
[AlphaISA::IPR_IFAULT_VA_FORM
] =
274 ipr
[AlphaISA::IPR_IVPTBR
] | (VA_VPN(pc
) << 3);
280 AlphaITB::translate(MemReqPtr
&req
) const
282 InternalProcReg
*ipr
= req
->xc
->regs
.ipr
;
284 if (PC_PAL(req
->vaddr
)) {
285 // strip off PAL PC marker (lsb is 1)
286 req
->paddr
= (req
->vaddr
& ~3) & PA_IMPL_MASK
;
291 if (req
->flags
& PHYSICAL
) {
292 req
->paddr
= req
->vaddr
;
294 // verify that this is a good virtual address
295 if (!validVirtualAddress(req
->vaddr
)) {
296 fault(req
->vaddr
, req
->xc
);
298 return ITB_Acv_Fault
;
302 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
303 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
304 if (VA_SPACE_EV6(req
->vaddr
) == 0x7e) {
306 // only valid in kernel mode
307 if (ICM_CM(ipr
[AlphaISA::IPR_ICM
]) != AlphaISA::mode_kernel
) {
308 fault(req
->vaddr
, req
->xc
);
310 return ITB_Acv_Fault
;
313 req
->paddr
= req
->vaddr
& PA_IMPL_MASK
;
315 // sign extend the physical address properly
316 if (req
->paddr
& PA_UNCACHED_BIT_40
)
317 req
->paddr
|= ULL(0xf0000000000);
319 req
->paddr
&= ULL(0xffffffffff);
322 // not a physical address: need to look up pte
323 AlphaISA::PTE
*pte
= lookup(VA_VPN(req
->vaddr
),
324 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
327 fault(req
->vaddr
, req
->xc
);
329 return ITB_Fault_Fault
;
332 req
->paddr
= PA_PFN2PA(pte
->ppn
) + VA_POFS(req
->vaddr
& ~3);
334 // check permissions for this access
335 if (!(pte
->xre
& (1 << ICM_CM(ipr
[AlphaISA::IPR_ICM
])))) {
336 // instruction access fault
337 fault(req
->vaddr
, req
->xc
);
339 return ITB_Acv_Fault
;
346 // check that the physical address is ok (catch bad physical addresses)
347 if (req
->paddr
& ~PA_IMPL_MASK
)
348 return Machine_Check_Fault
;
350 checkCacheability(req
);
355 ///////////////////////////////////////////////////////////////////////
359 AlphaDTB::AlphaDTB(const std::string
&name
, int size
)
360 : AlphaTLB(name
, size
)
367 .name(name() + ".read_hits")
368 .desc("DTB read hits")
372 .name(name() + ".read_misses")
373 .desc("DTB read misses")
377 .name(name() + ".read_acv")
378 .desc("DTB read access violations")
382 .name(name() + ".read_accesses")
383 .desc("DTB read accesses")
387 .name(name() + ".write_hits")
388 .desc("DTB write hits")
392 .name(name() + ".write_misses")
393 .desc("DTB write misses")
397 .name(name() + ".write_acv")
398 .desc("DTB write access violations")
402 .name(name() + ".write_accesses")
403 .desc("DTB write accesses")
407 .name(name() + ".hits")
412 .name(name() + ".misses")
417 .name(name() + ".acv")
418 .desc("DTB access violations")
422 .name(name() + ".accesses")
423 .desc("DTB accesses")
426 hits
= read_hits
+ write_hits
;
427 misses
= read_misses
+ write_misses
;
428 acv
= read_acv
+ write_acv
;
429 accesses
= read_accesses
+ write_accesses
;
433 AlphaDTB::fault(Addr vaddr
, uint64_t flags
, ExecContext
*xc
) const
435 uint64_t *ipr
= xc
->regs
.ipr
;
437 // set fault address and flags
438 if (!xc
->misspeculating() && !xc
->regs
.intrlock
) {
439 // set VA register with faulting address
440 ipr
[AlphaISA::IPR_VA
] = vaddr
;
442 // set MM_STAT register flags
443 ipr
[AlphaISA::IPR_MM_STAT
] = (((OPCODE(xc
->getInst()) & 0x3f) << 11)
444 | ((RA(xc
->getInst()) & 0x1f) << 6)
447 // set VA_FORM register with faulting formatted address
448 ipr
[AlphaISA::IPR_VA_FORM
] =
449 ipr
[AlphaISA::IPR_MVPTBR
] | (VA_VPN(vaddr
) << 3);
451 // lock these registers until the VA register is read
452 xc
->regs
.intrlock
= true;
457 AlphaDTB::translate(MemReqPtr
&req
, bool write
) const
459 RegFile
*regs
= &req
->xc
->regs
;
461 InternalProcReg
*ipr
= regs
->ipr
;
463 AlphaISA::mode_type mode
=
464 (AlphaISA::mode_type
)DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]);
467 mode
= (req
->flags
& ALTMODE
) ?
468 (AlphaISA::mode_type
)ALT_MODE_AM(ipr
[AlphaISA::IPR_ALT_MODE
])
469 : AlphaISA::mode_kernel
;
472 if (req
->flags
& PHYSICAL
) {
473 req
->paddr
= req
->vaddr
;
475 // verify that this is a good virtual address
476 if (!validVirtualAddress(req
->vaddr
)) {
478 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_BAD_VA_MASK
|
482 if (write
) { write_acv
++; } else { read_acv
++; }
483 return DTB_Fault_Fault
;
486 // Check for "superpage" mapping
487 if (VA_SPACE_EV6(req
->vaddr
) == 0x7e) {
489 // only valid in kernel mode
490 if (DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]) !=
491 AlphaISA::mode_kernel
) {
493 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_ACV_MASK
),
495 if (write
) { write_acv
++; } else { read_acv
++; }
496 return DTB_Acv_Fault
;
499 req
->paddr
= req
->vaddr
& PA_IMPL_MASK
;
501 // sign extend the physical address properly
502 if (req
->paddr
& PA_UNCACHED_BIT_40
)
503 req
->paddr
|= ULL(0xf0000000000);
505 req
->paddr
&= ULL(0xffffffffff);
513 // not a physical address: need to look up pte
514 AlphaISA::PTE
*pte
= lookup(VA_VPN(req
->vaddr
),
515 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
520 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_DTB_MISS_MASK
),
522 if (write
) { write_misses
++; } else { read_misses
++; }
523 return (req
->flags
& VPTE
) ? Pdtb_Miss_Fault
: Ndtb_Miss_Fault
;
526 req
->paddr
= PA_PFN2PA(pte
->ppn
) | VA_POFS(req
->vaddr
);
529 if (!(pte
->xwe
& MODE2MASK(mode
))) {
530 // declare the instruction access fault
531 fault(req
->vaddr
, MM_STAT_WR_MASK
| MM_STAT_ACV_MASK
|
532 (pte
->fonw
? MM_STAT_FONW_MASK
: 0),
535 return DTB_Fault_Fault
;
538 fault(req
->vaddr
, MM_STAT_WR_MASK
| MM_STAT_FONW_MASK
,
541 return DTB_Fault_Fault
;
544 if (!(pte
->xre
& MODE2MASK(mode
))) {
547 (pte
->fonr
? MM_STAT_FONR_MASK
: 0),
550 return DTB_Acv_Fault
;
553 fault(req
->vaddr
, MM_STAT_FONR_MASK
, req
->xc
);
555 return DTB_Fault_Fault
;
566 // check that the physical address is ok (catch bad physical addresses)
567 if (req
->paddr
& ~PA_IMPL_MASK
)
568 return Machine_Check_Fault
;
570 checkCacheability(req
);
576 AlphaTLB::index(bool advance
)
578 AlphaISA::PTE
*pte
= &table
[nlu
];
586 DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB
)
588 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB
)
592 END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB
)
594 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB
)
596 INIT_PARAM_DFLT(size
, "TLB size", 48)
598 END_INIT_SIM_OBJECT_PARAMS(AlphaITB
)
601 CREATE_SIM_OBJECT(AlphaITB
)
603 return new AlphaITB(getInstanceName(), size
);
606 REGISTER_SIM_OBJECT("AlphaITB", AlphaITB
)
608 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB
)
612 END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB
)
614 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB
)
616 INIT_PARAM_DFLT(size
, "TLB size", 64)
618 END_INIT_SIM_OBJECT_PARAMS(AlphaDTB
)
621 CREATE_SIM_OBJECT(AlphaDTB
)
623 return new AlphaDTB(getInstanceName(), size
);
626 REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB
)