2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "arch/alpha/alpha_memory.hh"
34 #include "base/inifile.hh"
35 #include "base/str.hh"
36 #include "base/trace.hh"
37 #include "config/alpha_tlaser.hh"
38 #include "cpu/exec_context.hh"
39 #include "sim/builder.hh"
44 ///////////////////////////////////////////////////////////////////////
49 bool uncacheBit39
= false;
50 bool uncacheBit40
= false;
53 #define MODE2MASK(X) (1 << (X))
55 AlphaTLB::AlphaTLB(const string
&name
, int s
)
56 : SimObject(name
), size(s
), nlu(0)
58 table
= new AlphaISA::PTE
[size
];
59 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
68 // look up an entry in the TLB
70 AlphaTLB::lookup(Addr vpn
, uint8_t asn
) const
72 // assume not found...
73 AlphaISA::PTE
*retval
= NULL
;
75 PageTable::const_iterator i
= lookupTable
.find(vpn
);
76 if (i
!= lookupTable
.end()) {
77 while (i
->first
== vpn
) {
78 int index
= i
->second
;
79 AlphaISA::PTE
*pte
= &table
[index
];
81 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
)) {
90 DPRINTF(TLB
, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn
, (int)asn
,
91 retval
? "hit" : "miss", retval
? retval
->ppn
: 0);
97 AlphaTLB::checkCacheability(MemReqPtr
&req
)
99 // in Alpha, cacheability is controlled by upper-level bits of the
103 * We support having the uncacheable bit in either bit 39 or bit 40.
104 * The Turbolaser platform (and EV5) support having the bit in 39, but
105 * Tsunami (which Linux assumes uses an EV6) generates accesses with
106 * the bit in 40. So we must check for both, but we have debug flags
107 * to catch a weird case where both are used, which shouldn't happen.
112 if (req
->paddr
& PAddrUncachedBit39
) {
114 if (req
->paddr
& PAddrUncachedBit43
) {
116 // IPR memory space not implemented
117 if (PAddrIprSpace(req
->paddr
)) {
118 if (!req
->xc
->misspeculating()) {
119 switch (req
->paddr
) {
120 case ULL(0xFFFFF00188):
125 panic("IPR memory space not implemented! PA=%x\n",
130 // mark request as uncacheable
131 req
->flags
|= UNCACHEABLE
;
134 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
135 req
->paddr
&= PAddrUncachedMask
;
142 // insert a new TLB entry
144 AlphaTLB::insert(Addr addr
, AlphaISA::PTE
&pte
)
146 AlphaISA::VAddr vaddr
= addr
;
147 if (table
[nlu
].valid
) {
148 Addr oldvpn
= table
[nlu
].tag
;
149 PageTable::iterator i
= lookupTable
.find(oldvpn
);
151 if (i
== lookupTable
.end())
152 panic("TLB entry not found in lookupTable");
155 while ((index
= i
->second
) != nlu
) {
156 if (table
[index
].tag
!= oldvpn
)
157 panic("TLB entry not found in lookupTable");
162 DPRINTF(TLB
, "remove @%d: %#x -> %#x\n", nlu
, oldvpn
, table
[nlu
].ppn
);
164 lookupTable
.erase(i
);
167 DPRINTF(TLB
, "insert @%d: %#x -> %#x\n", nlu
, vaddr
.vpn(), pte
.ppn
);
170 table
[nlu
].tag
= vaddr
.vpn();
171 table
[nlu
].valid
= true;
173 lookupTable
.insert(make_pair(vaddr
.vpn(), nlu
));
180 DPRINTF(TLB
, "flushAll\n");
181 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
187 AlphaTLB::flushProcesses()
189 PageTable::iterator i
= lookupTable
.begin();
190 PageTable::iterator end
= lookupTable
.end();
192 int index
= i
->second
;
193 AlphaISA::PTE
*pte
= &table
[index
];
196 // we can't increment i after we erase it, so save a copy and
197 // increment it to get the next entry now
198 PageTable::iterator cur
= i
;
202 DPRINTF(TLB
, "flush @%d: %#x -> %#x\n", index
, pte
->tag
, pte
->ppn
);
204 lookupTable
.erase(cur
);
210 AlphaTLB::flushAddr(Addr addr
, uint8_t asn
)
212 AlphaISA::VAddr vaddr
= addr
;
214 PageTable::iterator i
= lookupTable
.find(vaddr
.vpn());
215 if (i
== lookupTable
.end())
218 while (i
->first
== vaddr
.vpn()) {
219 int index
= i
->second
;
220 AlphaISA::PTE
*pte
= &table
[index
];
223 if (vaddr
.vpn() == pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
)) {
224 DPRINTF(TLB
, "flushaddr @%d: %#x -> %#x\n", index
, vaddr
.vpn(),
227 // invalidate this entry
230 lookupTable
.erase(i
);
239 AlphaTLB::serialize(ostream
&os
)
241 SERIALIZE_SCALAR(size
);
242 SERIALIZE_SCALAR(nlu
);
244 for (int i
= 0; i
< size
; i
++) {
245 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
246 table
[i
].serialize(os
);
251 AlphaTLB::unserialize(Checkpoint
*cp
, const string
§ion
)
253 UNSERIALIZE_SCALAR(size
);
254 UNSERIALIZE_SCALAR(nlu
);
256 for (int i
= 0; i
< size
; i
++) {
257 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
258 if (table
[i
].valid
) {
259 lookupTable
.insert(make_pair(table
[i
].tag
, i
));
265 ///////////////////////////////////////////////////////////////////////
269 AlphaITB::AlphaITB(const std::string
&name
, int size
)
270 : AlphaTLB(name
, size
)
278 .name(name() + ".hits")
281 .name(name() + ".misses")
284 .name(name() + ".acv")
287 .name(name() + ".accesses")
288 .desc("ITB accesses");
290 accesses
= hits
+ misses
;
294 AlphaITB::fault(Addr pc
, ExecContext
*xc
) const
296 uint64_t *ipr
= xc
->regs
.ipr
;
298 if (!xc
->misspeculating()) {
299 ipr
[AlphaISA::IPR_ITB_TAG
] = pc
;
300 ipr
[AlphaISA::IPR_IFAULT_VA_FORM
] =
301 ipr
[AlphaISA::IPR_IVPTBR
] | (AlphaISA::VAddr(pc
).vpn() << 3);
307 AlphaITB::translate(MemReqPtr
&req
) const
309 InternalProcReg
*ipr
= req
->xc
->regs
.ipr
;
311 if (AlphaISA::PcPAL(req
->vaddr
)) {
312 // strip off PAL PC marker (lsb is 1)
313 req
->paddr
= (req
->vaddr
& ~3) & PAddrImplMask
;
318 if (req
->flags
& PHYSICAL
) {
319 req
->paddr
= req
->vaddr
;
321 // verify that this is a good virtual address
322 if (!validVirtualAddress(req
->vaddr
)) {
323 fault(req
->vaddr
, req
->xc
);
325 return ITB_Acv_Fault
;
329 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
330 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
332 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) &&
333 VAddrSpaceEV5(req
->vaddr
) == 2) {
335 if (VAddrSpaceEV6(req
->vaddr
) == 0x7e) {
337 // only valid in kernel mode
338 if (ICM_CM(ipr
[AlphaISA::IPR_ICM
]) !=
339 AlphaISA::mode_kernel
) {
340 fault(req
->vaddr
, req
->xc
);
342 return ITB_Acv_Fault
;
345 req
->paddr
= req
->vaddr
& PAddrImplMask
;
348 // sign extend the physical address properly
349 if (req
->paddr
& PAddrUncachedBit40
)
350 req
->paddr
|= ULL(0xf0000000000);
352 req
->paddr
&= ULL(0xffffffffff);
356 // not a physical address: need to look up pte
357 AlphaISA::PTE
*pte
= lookup(AlphaISA::VAddr(req
->vaddr
).vpn(),
358 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
361 fault(req
->vaddr
, req
->xc
);
363 return ITB_Fault_Fault
;
366 req
->paddr
= (pte
->ppn
<< AlphaISA::PageShift
) +
367 (AlphaISA::VAddr(req
->vaddr
).offset() & ~3);
369 // check permissions for this access
370 if (!(pte
->xre
& (1 << ICM_CM(ipr
[AlphaISA::IPR_ICM
])))) {
371 // instruction access fault
372 fault(req
->vaddr
, req
->xc
);
374 return ITB_Acv_Fault
;
381 // check that the physical address is ok (catch bad physical addresses)
382 if (req
->paddr
& ~PAddrImplMask
)
383 return Machine_Check_Fault
;
385 checkCacheability(req
);
390 ///////////////////////////////////////////////////////////////////////
394 AlphaDTB::AlphaDTB(const std::string
&name
, int size
)
395 : AlphaTLB(name
, size
)
402 .name(name() + ".read_hits")
403 .desc("DTB read hits")
407 .name(name() + ".read_misses")
408 .desc("DTB read misses")
412 .name(name() + ".read_acv")
413 .desc("DTB read access violations")
417 .name(name() + ".read_accesses")
418 .desc("DTB read accesses")
422 .name(name() + ".write_hits")
423 .desc("DTB write hits")
427 .name(name() + ".write_misses")
428 .desc("DTB write misses")
432 .name(name() + ".write_acv")
433 .desc("DTB write access violations")
437 .name(name() + ".write_accesses")
438 .desc("DTB write accesses")
442 .name(name() + ".hits")
447 .name(name() + ".misses")
452 .name(name() + ".acv")
453 .desc("DTB access violations")
457 .name(name() + ".accesses")
458 .desc("DTB accesses")
461 hits
= read_hits
+ write_hits
;
462 misses
= read_misses
+ write_misses
;
463 acv
= read_acv
+ write_acv
;
464 accesses
= read_accesses
+ write_accesses
;
468 AlphaDTB::fault(MemReqPtr
&req
, uint64_t flags
) const
470 ExecContext
*xc
= req
->xc
;
471 AlphaISA::VAddr vaddr
= req
->vaddr
;
472 uint64_t *ipr
= xc
->regs
.ipr
;
474 // Set fault address and flags. Even though we're modeling an
475 // EV5, we use the EV6 technique of not latching fault registers
476 // on VPTE loads (instead of locking the registers until IPR_VA is
477 // read, like the EV5). The EV6 approach is cleaner and seems to
478 // work with EV5 PAL code, but not the other way around.
479 if (!xc
->misspeculating()
480 && !(req
->flags
& VPTE
) && !(req
->flags
& NO_FAULT
)) {
481 // set VA register with faulting address
482 ipr
[AlphaISA::IPR_VA
] = req
->vaddr
;
484 // set MM_STAT register flags
485 ipr
[AlphaISA::IPR_MM_STAT
] =
486 (((Opcode(xc
->getInst()) & 0x3f) << 11)
487 | ((Ra(xc
->getInst()) & 0x1f) << 6)
490 // set VA_FORM register with faulting formatted address
491 ipr
[AlphaISA::IPR_VA_FORM
] =
492 ipr
[AlphaISA::IPR_MVPTBR
] | (vaddr
.vpn() << 3);
497 AlphaDTB::translate(MemReqPtr
&req
, bool write
) const
499 RegFile
*regs
= &req
->xc
->regs
;
501 InternalProcReg
*ipr
= regs
->ipr
;
503 AlphaISA::mode_type mode
=
504 (AlphaISA::mode_type
)DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]);
508 * Check for alignment faults
510 if (req
->vaddr
& (req
->size
- 1)) {
511 fault(req
, write
? MM_STAT_WR_MASK
: 0);
512 DPRINTF(TLB
, "Alignment Fault on %#x, size = %d", req
->vaddr
,
514 return Alignment_Fault
;
518 mode
= (req
->flags
& ALTMODE
) ?
519 (AlphaISA::mode_type
)ALT_MODE_AM(ipr
[AlphaISA::IPR_ALT_MODE
])
520 : AlphaISA::mode_kernel
;
523 if (req
->flags
& PHYSICAL
) {
524 req
->paddr
= req
->vaddr
;
526 // verify that this is a good virtual address
527 if (!validVirtualAddress(req
->vaddr
)) {
528 fault(req
, (write
? MM_STAT_WR_MASK
: 0) |
529 MM_STAT_BAD_VA_MASK
|
532 if (write
) { write_acv
++; } else { read_acv
++; }
533 return DTB_Fault_Fault
;
536 // Check for "superpage" mapping
538 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) &&
539 VAddrSpaceEV5(req
->vaddr
) == 2) {
541 if (VAddrSpaceEV6(req
->vaddr
) == 0x7e) {
544 // only valid in kernel mode
545 if (DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]) !=
546 AlphaISA::mode_kernel
) {
547 fault(req
, ((write
? MM_STAT_WR_MASK
: 0) |
549 if (write
) { write_acv
++; } else { read_acv
++; }
550 return DTB_Acv_Fault
;
553 req
->paddr
= req
->vaddr
& PAddrImplMask
;
556 // sign extend the physical address properly
557 if (req
->paddr
& PAddrUncachedBit40
)
558 req
->paddr
|= ULL(0xf0000000000);
560 req
->paddr
&= ULL(0xffffffffff);
569 // not a physical address: need to look up pte
570 AlphaISA::PTE
*pte
= lookup(AlphaISA::VAddr(req
->vaddr
).vpn(),
571 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
575 fault(req
, (write
? MM_STAT_WR_MASK
: 0) |
576 MM_STAT_DTB_MISS_MASK
);
577 if (write
) { write_misses
++; } else { read_misses
++; }
578 return (req
->flags
& VPTE
) ? Pdtb_Miss_Fault
: Ndtb_Miss_Fault
;
581 req
->paddr
= (pte
->ppn
<< AlphaISA::PageShift
) +
582 AlphaISA::VAddr(req
->vaddr
).offset();
585 if (!(pte
->xwe
& MODE2MASK(mode
))) {
586 // declare the instruction access fault
587 fault(req
, MM_STAT_WR_MASK
|
589 (pte
->fonw
? MM_STAT_FONW_MASK
: 0));
591 return DTB_Fault_Fault
;
594 fault(req
, MM_STAT_WR_MASK
|
597 return DTB_Fault_Fault
;
600 if (!(pte
->xre
& MODE2MASK(mode
))) {
601 fault(req
, MM_STAT_ACV_MASK
|
602 (pte
->fonr
? MM_STAT_FONR_MASK
: 0));
604 return DTB_Acv_Fault
;
607 fault(req
, MM_STAT_FONR_MASK
);
609 return DTB_Fault_Fault
;
620 // check that the physical address is ok (catch bad physical addresses)
621 if (req
->paddr
& ~PAddrImplMask
)
622 return Machine_Check_Fault
;
624 checkCacheability(req
);
630 AlphaTLB::index(bool advance
)
632 AlphaISA::PTE
*pte
= &table
[nlu
];
640 DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB
)
642 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB
)
646 END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB
)
648 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB
)
650 INIT_PARAM_DFLT(size
, "TLB size", 48)
652 END_INIT_SIM_OBJECT_PARAMS(AlphaITB
)
655 CREATE_SIM_OBJECT(AlphaITB
)
657 return new AlphaITB(getInstanceName(), size
);
660 REGISTER_SIM_OBJECT("AlphaITB", AlphaITB
)
662 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB
)
666 END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB
)
668 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB
)
670 INIT_PARAM_DFLT(size
, "TLB size", 64)
672 END_INIT_SIM_OBJECT_PARAMS(AlphaDTB
)
675 CREATE_SIM_OBJECT(AlphaDTB
)
677 return new AlphaDTB(getInstanceName(), size
);
680 REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB
)