2 * Copyright (c) 2001-2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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33 #include "arch/alpha/alpha_memory.hh"
34 #include "base/inifile.hh"
35 #include "base/str.hh"
36 #include "base/trace.hh"
37 #include "cpu/exec_context.hh"
38 #include "sim/builder.hh"
43 ///////////////////////////////////////////////////////////////////////
48 bool uncacheBit39
= false;
49 bool uncacheBit40
= false;
52 #define MODE2MASK(X) (1 << (X))
54 AlphaTLB::AlphaTLB(const string
&name
, int s
)
55 : SimObject(name
), size(s
), nlu(0)
57 table
= new AlphaISA::PTE
[size
];
58 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
67 // look up an entry in the TLB
69 AlphaTLB::lookup(Addr vpn
, uint8_t asn
) const
71 DPRINTF(TLB
, "lookup %#x, asn %#x\n", vpn
, (int)asn
);
73 PageTable::const_iterator i
= lookupTable
.find(vpn
);
74 if (i
== lookupTable
.end())
77 while (i
->first
== vpn
) {
78 int index
= i
->second
;
79 AlphaISA::PTE
*pte
= &table
[index
];
81 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
))
93 AlphaTLB::checkCacheability(MemReqPtr
&req
)
95 // in Alpha, cacheability is controlled by upper-level bits of the
99 * We support having the uncacheable bit in either bit 39 or bit 40.
100 * The Turbolaser platform (and EV5) support having the bit in 39, but
101 * Tsunami (which Linux assumes uses an EV6) generates accesses with
102 * the bit in 40. So we must check for both, but we have debug flags
103 * to catch a weird case where both are used, which shouldn't happen.
108 if (req
->paddr
& PAddrUncachedBit39
) {
110 if (req
->paddr
& PAddrUncachedBit43
) {
112 // IPR memory space not implemented
113 if (PAddrIprSpace(req
->paddr
)) {
114 if (!req
->xc
->misspeculating()) {
115 switch (req
->paddr
) {
116 case ULL(0xFFFFF00188):
121 panic("IPR memory space not implemented! PA=%x\n",
126 // mark request as uncacheable
127 req
->flags
|= UNCACHEABLE
;
130 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
131 req
->paddr
&= PAddrUncachedMask
;
138 // insert a new TLB entry
140 AlphaTLB::insert(Addr addr
, AlphaISA::PTE
&pte
)
142 AlphaISA::VAddr vaddr
= addr
;
143 if (table
[nlu
].valid
) {
144 Addr oldvpn
= table
[nlu
].tag
;
145 PageTable::iterator i
= lookupTable
.find(oldvpn
);
147 if (i
== lookupTable
.end())
148 panic("TLB entry not found in lookupTable");
151 while ((index
= i
->second
) != nlu
) {
152 if (table
[index
].tag
!= oldvpn
)
153 panic("TLB entry not found in lookupTable");
158 DPRINTF(TLB
, "remove @%d: %#x -> %#x\n", nlu
, oldvpn
, table
[nlu
].ppn
);
160 lookupTable
.erase(i
);
163 DPRINTF(TLB
, "insert @%d: %#x -> %#x\n", nlu
, vaddr
.vpn(), pte
.ppn
);
166 table
[nlu
].tag
= vaddr
.vpn();
167 table
[nlu
].valid
= true;
169 lookupTable
.insert(make_pair(vaddr
.vpn(), nlu
));
176 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
182 AlphaTLB::flushProcesses()
184 PageTable::iterator i
= lookupTable
.begin();
185 PageTable::iterator end
= lookupTable
.end();
187 int index
= i
->second
;
188 AlphaISA::PTE
*pte
= &table
[index
];
192 DPRINTF(TLB
, "flush @%d: %#x -> %#x\n", index
, pte
->tag
, pte
->ppn
);
194 lookupTable
.erase(i
);
202 AlphaTLB::flushAddr(Addr addr
, uint8_t asn
)
204 AlphaISA::VAddr vaddr
= addr
;
206 PageTable::iterator i
= lookupTable
.find(vaddr
.vpn());
207 if (i
== lookupTable
.end())
210 while (i
->first
== vaddr
.vpn()) {
211 int index
= i
->second
;
212 AlphaISA::PTE
*pte
= &table
[index
];
215 if (vaddr
.vpn() == pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
)) {
216 DPRINTF(TLB
, "flushaddr @%d: %#x -> %#x\n", index
, vaddr
.vpn(),
219 // invalidate this entry
222 lookupTable
.erase(i
);
231 AlphaTLB::serialize(ostream
&os
)
233 SERIALIZE_SCALAR(size
);
234 SERIALIZE_SCALAR(nlu
);
236 for (int i
= 0; i
< size
; i
++) {
237 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
238 table
[i
].serialize(os
);
243 AlphaTLB::unserialize(Checkpoint
*cp
, const string
§ion
)
245 UNSERIALIZE_SCALAR(size
);
246 UNSERIALIZE_SCALAR(nlu
);
248 for (int i
= 0; i
< size
; i
++) {
249 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
250 if (table
[i
].valid
) {
251 lookupTable
.insert(make_pair(table
[i
].tag
, i
));
257 ///////////////////////////////////////////////////////////////////////
261 AlphaITB::AlphaITB(const std::string
&name
, int size
)
262 : AlphaTLB(name
, size
)
270 .name(name() + ".hits")
273 .name(name() + ".misses")
276 .name(name() + ".acv")
279 .name(name() + ".accesses")
280 .desc("ITB accesses");
282 accesses
= hits
+ misses
;
286 AlphaITB::fault(Addr pc
, ExecContext
*xc
) const
288 uint64_t *ipr
= xc
->regs
.ipr
;
290 if (!xc
->misspeculating()) {
291 ipr
[AlphaISA::IPR_ITB_TAG
] = pc
;
292 ipr
[AlphaISA::IPR_IFAULT_VA_FORM
] =
293 ipr
[AlphaISA::IPR_IVPTBR
] | (AlphaISA::VAddr(pc
).vpn() << 3);
299 AlphaITB::translate(MemReqPtr
&req
) const
301 InternalProcReg
*ipr
= req
->xc
->regs
.ipr
;
303 if (AlphaISA::PcPAL(req
->vaddr
)) {
304 // strip off PAL PC marker (lsb is 1)
305 req
->paddr
= (req
->vaddr
& ~3) & PAddrImplMask
;
310 if (req
->flags
& PHYSICAL
) {
311 req
->paddr
= req
->vaddr
;
313 // verify that this is a good virtual address
314 if (!validVirtualAddress(req
->vaddr
)) {
315 fault(req
->vaddr
, req
->xc
);
317 return ITB_Acv_Fault
;
321 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
322 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
324 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) &&
325 VAddrSpaceEV5(req
->vaddr
) == 2) {
327 if (VAddrSpaceEV6(req
->vaddr
) == 0x7e) {
329 // only valid in kernel mode
330 if (ICM_CM(ipr
[AlphaISA::IPR_ICM
]) !=
331 AlphaISA::mode_kernel
) {
332 fault(req
->vaddr
, req
->xc
);
334 return ITB_Acv_Fault
;
337 req
->paddr
= req
->vaddr
& PAddrImplMask
;
340 // sign extend the physical address properly
341 if (req
->paddr
& PAddrUncachedBit40
)
342 req
->paddr
|= ULL(0xf0000000000);
344 req
->paddr
&= ULL(0xffffffffff);
348 // not a physical address: need to look up pte
349 AlphaISA::PTE
*pte
= lookup(AlphaISA::VAddr(req
->vaddr
).vpn(),
350 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
353 fault(req
->vaddr
, req
->xc
);
355 return ITB_Fault_Fault
;
358 req
->paddr
= (pte
->ppn
<< AlphaISA::PageShift
) +
359 (AlphaISA::VAddr(req
->vaddr
).offset() & ~3);
361 // check permissions for this access
362 if (!(pte
->xre
& (1 << ICM_CM(ipr
[AlphaISA::IPR_ICM
])))) {
363 // instruction access fault
364 fault(req
->vaddr
, req
->xc
);
366 return ITB_Acv_Fault
;
373 // check that the physical address is ok (catch bad physical addresses)
374 if (req
->paddr
& ~PAddrImplMask
)
375 return Machine_Check_Fault
;
377 checkCacheability(req
);
382 ///////////////////////////////////////////////////////////////////////
386 AlphaDTB::AlphaDTB(const std::string
&name
, int size
)
387 : AlphaTLB(name
, size
)
394 .name(name() + ".read_hits")
395 .desc("DTB read hits")
399 .name(name() + ".read_misses")
400 .desc("DTB read misses")
404 .name(name() + ".read_acv")
405 .desc("DTB read access violations")
409 .name(name() + ".read_accesses")
410 .desc("DTB read accesses")
414 .name(name() + ".write_hits")
415 .desc("DTB write hits")
419 .name(name() + ".write_misses")
420 .desc("DTB write misses")
424 .name(name() + ".write_acv")
425 .desc("DTB write access violations")
429 .name(name() + ".write_accesses")
430 .desc("DTB write accesses")
434 .name(name() + ".hits")
439 .name(name() + ".misses")
444 .name(name() + ".acv")
445 .desc("DTB access violations")
449 .name(name() + ".accesses")
450 .desc("DTB accesses")
453 hits
= read_hits
+ write_hits
;
454 misses
= read_misses
+ write_misses
;
455 acv
= read_acv
+ write_acv
;
456 accesses
= read_accesses
+ write_accesses
;
460 AlphaDTB::fault(MemReqPtr
&req
, uint64_t flags
) const
462 ExecContext
*xc
= req
->xc
;
463 AlphaISA::VAddr vaddr
= req
->vaddr
;
464 uint64_t *ipr
= xc
->regs
.ipr
;
466 // Set fault address and flags. Even though we're modeling an
467 // EV5, we use the EV6 technique of not latching fault registers
468 // on VPTE loads (instead of locking the registers until IPR_VA is
469 // read, like the EV5). The EV6 approach is cleaner and seems to
470 // work with EV5 PAL code, but not the other way around.
471 if (!xc
->misspeculating()
472 && !(req
->flags
& VPTE
) && !(req
->flags
& NO_FAULT
)) {
473 // set VA register with faulting address
474 ipr
[AlphaISA::IPR_VA
] = req
->vaddr
;
476 // set MM_STAT register flags
477 ipr
[AlphaISA::IPR_MM_STAT
] =
478 (((Opcode(xc
->getInst()) & 0x3f) << 11)
479 | ((Ra(xc
->getInst()) & 0x1f) << 6)
482 // set VA_FORM register with faulting formatted address
483 ipr
[AlphaISA::IPR_VA_FORM
] =
484 ipr
[AlphaISA::IPR_MVPTBR
] | (vaddr
.vpn() << 3);
489 AlphaDTB::translate(MemReqPtr
&req
, bool write
) const
491 RegFile
*regs
= &req
->xc
->regs
;
493 InternalProcReg
*ipr
= regs
->ipr
;
495 AlphaISA::mode_type mode
=
496 (AlphaISA::mode_type
)DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]);
500 * Check for alignment faults
502 if (req
->vaddr
& (req
->size
- 1)) {
503 fault(req
, write
? MM_STAT_WR_MASK
: 0);
504 return Alignment_Fault
;
508 mode
= (req
->flags
& ALTMODE
) ?
509 (AlphaISA::mode_type
)ALT_MODE_AM(ipr
[AlphaISA::IPR_ALT_MODE
])
510 : AlphaISA::mode_kernel
;
513 if (req
->flags
& PHYSICAL
) {
514 req
->paddr
= req
->vaddr
;
516 // verify that this is a good virtual address
517 if (!validVirtualAddress(req
->vaddr
)) {
518 fault(req
, (write
? MM_STAT_WR_MASK
: 0) |
519 MM_STAT_BAD_VA_MASK
|
522 if (write
) { write_acv
++; } else { read_acv
++; }
523 return DTB_Fault_Fault
;
526 // Check for "superpage" mapping
528 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) &&
529 VAddrSpaceEV5(req
->vaddr
) == 2) {
531 if (VAddrSpaceEV6(req
->vaddr
) == 0x7e) {
534 // only valid in kernel mode
535 if (DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]) !=
536 AlphaISA::mode_kernel
) {
537 fault(req
, ((write
? MM_STAT_WR_MASK
: 0) |
539 if (write
) { write_acv
++; } else { read_acv
++; }
540 return DTB_Acv_Fault
;
543 req
->paddr
= req
->vaddr
& PAddrImplMask
;
546 // sign extend the physical address properly
547 if (req
->paddr
& PAddrUncachedBit40
)
548 req
->paddr
|= ULL(0xf0000000000);
550 req
->paddr
&= ULL(0xffffffffff);
559 // not a physical address: need to look up pte
560 AlphaISA::PTE
*pte
= lookup(AlphaISA::VAddr(req
->vaddr
).vpn(),
561 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
565 fault(req
, (write
? MM_STAT_WR_MASK
: 0) |
566 MM_STAT_DTB_MISS_MASK
);
567 if (write
) { write_misses
++; } else { read_misses
++; }
568 return (req
->flags
& VPTE
) ? Pdtb_Miss_Fault
: Ndtb_Miss_Fault
;
571 req
->paddr
= (pte
->ppn
<< AlphaISA::PageShift
) +
572 AlphaISA::VAddr(req
->vaddr
).offset();
575 if (!(pte
->xwe
& MODE2MASK(mode
))) {
576 // declare the instruction access fault
577 fault(req
, MM_STAT_WR_MASK
|
579 (pte
->fonw
? MM_STAT_FONW_MASK
: 0));
581 return DTB_Fault_Fault
;
584 fault(req
, MM_STAT_WR_MASK
|
587 return DTB_Fault_Fault
;
590 if (!(pte
->xre
& MODE2MASK(mode
))) {
591 fault(req
, MM_STAT_ACV_MASK
|
592 (pte
->fonr
? MM_STAT_FONR_MASK
: 0));
594 return DTB_Acv_Fault
;
597 fault(req
, MM_STAT_FONR_MASK
);
599 return DTB_Fault_Fault
;
610 // check that the physical address is ok (catch bad physical addresses)
611 if (req
->paddr
& ~PAddrImplMask
)
612 return Machine_Check_Fault
;
614 checkCacheability(req
);
620 AlphaTLB::index(bool advance
)
622 AlphaISA::PTE
*pte
= &table
[nlu
];
630 DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB
)
632 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB
)
636 END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB
)
638 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB
)
640 INIT_PARAM_DFLT(size
, "TLB size", 48)
642 END_INIT_SIM_OBJECT_PARAMS(AlphaITB
)
645 CREATE_SIM_OBJECT(AlphaITB
)
647 return new AlphaITB(getInstanceName(), size
);
650 REGISTER_SIM_OBJECT("AlphaITB", AlphaITB
)
652 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB
)
656 END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB
)
658 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB
)
660 INIT_PARAM_DFLT(size
, "TLB size", 64)
662 END_INIT_SIM_OBJECT_PARAMS(AlphaDTB
)
665 CREATE_SIM_OBJECT(AlphaDTB
)
667 return new AlphaDTB(getInstanceName(), size
);
670 REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB
)