2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "base/inifile.hh"
34 #include "base/str.hh"
35 #include "base/trace.hh"
36 #include "cpu/exec_context.hh"
37 #include "sim/builder.hh"
38 #include "targetarch/alpha_memory.hh"
39 #include "targetarch/ev5.hh"
43 ///////////////////////////////////////////////////////////////////////
47 AlphaTlb::AlphaTlb(const string
&name
, int s
)
48 : SimObject(name
), size(s
), nlu(0)
50 table
= new AlphaISA::PTE
[size
];
51 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
60 // look up an entry in the TLB
62 AlphaTlb::lookup(Addr vpn
, uint8_t asn
) const
64 DPRINTF(TLB
, "lookup %#x\n", vpn
);
66 PageTable::const_iterator i
= lookupTable
.find(vpn
);
67 if (i
== lookupTable
.end())
70 while (i
->first
== vpn
) {
71 int index
= i
->second
;
72 AlphaISA::PTE
*pte
= &table
[index
];
74 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
))
86 AlphaTlb::checkCacheability(MemReqPtr
&req
)
88 // in Alpha, cacheability is controlled by upper-level bits of the
90 if (req
->paddr
& PA_UNCACHED_BIT
) {
91 if (PA_IPR_SPACE(req
->paddr
)) {
92 // IPR memory space not implemented
93 if (!req
->xc
->misspeculating()) {
100 panic("IPR memory space not implemented! PA=%x\n", req
->paddr
);
104 // mark request as uncacheable
105 req
->flags
|= UNCACHEABLE
;
111 // insert a new TLB entry
113 AlphaTlb::insert(Addr vaddr
, AlphaISA::PTE
&pte
)
115 if (table
[nlu
].valid
) {
116 Addr oldvpn
= table
[nlu
].tag
;
117 PageTable::iterator i
= lookupTable
.find(oldvpn
);
119 if (i
== lookupTable
.end())
120 panic("TLB entry not found in lookupTable");
123 while ((index
= i
->second
) != nlu
) {
124 if (table
[index
].tag
!= oldvpn
)
125 panic("TLB entry not found in lookupTable");
130 DPRINTF(TLB
, "remove @%d: %#x -> %#x\n", nlu
, oldvpn
, table
[nlu
].ppn
);
132 lookupTable
.erase(i
);
135 Addr vpn
= VA_VPN(vaddr
);
136 DPRINTF(TLB
, "insert @%d: %#x -> %#x\n", nlu
, vpn
, pte
.ppn
);
139 table
[nlu
].tag
= vpn
;
140 table
[nlu
].valid
= true;
142 lookupTable
.insert(make_pair(vpn
, nlu
));
149 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
155 AlphaTlb::flushProcesses()
157 PageTable::iterator i
= lookupTable
.begin();
158 PageTable::iterator end
= lookupTable
.end();
160 int index
= i
->second
;
161 AlphaISA::PTE
*pte
= &table
[index
];
165 DPRINTF(TLB
, "flush @%d: %#x -> %#x\n", index
, pte
->tag
, pte
->ppn
);
167 lookupTable
.erase(i
);
175 AlphaTlb::flushAddr(Addr vaddr
, uint8_t asn
)
177 Addr vpn
= VA_VPN(vaddr
);
179 PageTable::iterator i
= lookupTable
.find(vpn
);
180 if (i
== lookupTable
.end())
183 while (i
->first
== vpn
) {
184 int index
= i
->second
;
185 AlphaISA::PTE
*pte
= &table
[index
];
188 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
)) {
189 DPRINTF(TLB
, "flushaddr @%d: %#x -> %#x\n", index
, vpn
, pte
->ppn
);
191 // invalidate this entry
194 lookupTable
.erase(i
);
203 AlphaTlb::serialize(ostream
&os
)
205 SERIALIZE_SCALAR(size
);
206 SERIALIZE_SCALAR(nlu
);
208 for (int i
= 0; i
< size
; i
++) {
209 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
210 table
[i
].serialize(os
);
215 AlphaTlb::unserialize(Checkpoint
*cp
, const string
§ion
)
217 UNSERIALIZE_SCALAR(size
);
218 UNSERIALIZE_SCALAR(nlu
);
220 for (int i
= 0; i
< size
; i
++) {
221 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
222 if (table
[i
].valid
) {
223 lookupTable
.insert(make_pair(table
[i
].tag
, i
));
229 ///////////////////////////////////////////////////////////////////////
233 AlphaItb::AlphaItb(const std::string
&name
, int size
)
234 : AlphaTlb(name
, size
)
242 .name(name() + ".hits")
245 .name(name() + ".misses")
248 .name(name() + ".acv")
251 .name(name() + ".accesses")
252 .desc("ITB accesses");
254 accesses
= hits
+ misses
;
258 AlphaItb::fault(Addr pc
, ExecContext
*xc
) const
260 uint64_t *ipr
= xc
->regs
.ipr
;
262 if (!xc
->misspeculating()) {
263 ipr
[AlphaISA::IPR_ITB_TAG
] = pc
;
264 ipr
[AlphaISA::IPR_IFAULT_VA_FORM
] =
265 ipr
[AlphaISA::IPR_IVPTBR
] | (VA_VPN(pc
) << 3);
271 AlphaItb::translate(MemReqPtr
&req
) const
273 InternalProcReg
*ipr
= req
->xc
->regs
.ipr
;
275 if (PC_PAL(req
->vaddr
)) {
276 // strip off PAL PC marker (lsb is 1)
277 req
->paddr
= (req
->vaddr
& ~3) & PA_IMPL_MASK
;
282 // verify that this is a good virtual address
283 if (!validVirtualAddress(req
->vaddr
)) {
284 fault(req
->vaddr
, req
->xc
);
286 return Itb_Acv_Fault
;
289 // Check for "superpage" mapping: when SP<1> is set, and
290 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
291 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) &&
292 VA_SPACE(req
->vaddr
) == 2) {
293 // only valid in kernel mode
294 if (ICM_CM(ipr
[AlphaISA::IPR_ICM
]) != AlphaISA::mode_kernel
) {
295 fault(req
->vaddr
, req
->xc
);
297 return Itb_Acv_Fault
;
300 req
->flags
|= PHYSICAL
;
303 if (req
->flags
& PHYSICAL
) {
304 req
->paddr
= req
->vaddr
& PA_IMPL_MASK
;
306 // not a physical address: need to look up pte
308 AlphaISA::PTE
*pte
= lookup(VA_VPN(req
->vaddr
),
309 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
312 fault(req
->vaddr
, req
->xc
);
314 return Itb_Fault_Fault
;
317 req
->paddr
= PA_PFN2PA(pte
->ppn
) + VA_POFS(req
->vaddr
& ~3);
319 // check permissions for this access
320 if (!(pte
->xre
& (1 << ICM_CM(ipr
[AlphaISA::IPR_ICM
])))) {
321 // instruction access fault
322 fault(req
->vaddr
, req
->xc
);
324 return Itb_Acv_Fault
;
328 checkCacheability(req
);
334 ///////////////////////////////////////////////////////////////////////
338 AlphaDtb::AlphaDtb(const std::string
&name
, int size
)
339 : AlphaTlb(name
, size
)
346 .name(name() + ".read_hits")
347 .desc("DTB read hits")
351 .name(name() + ".read_misses")
352 .desc("DTB read misses")
356 .name(name() + ".read_acv")
357 .desc("DTB read access violations")
361 .name(name() + ".read_accesses")
362 .desc("DTB read accesses")
366 .name(name() + ".write_hits")
367 .desc("DTB write hits")
371 .name(name() + ".write_misses")
372 .desc("DTB write misses")
376 .name(name() + ".write_acv")
377 .desc("DTB write access violations")
381 .name(name() + ".write_accesses")
382 .desc("DTB write accesses")
386 .name(name() + ".hits")
391 .name(name() + ".misses")
396 .name(name() + ".acv")
397 .desc("DTB access violations")
401 .name(name() + ".accesses")
402 .desc("DTB accesses")
405 hits
= read_hits
+ write_hits
;
406 misses
= read_misses
+ write_misses
;
407 acv
= read_acv
+ write_acv
;
408 accesses
= read_accesses
+ write_accesses
;
412 AlphaDtb::fault(Addr vaddr
, uint64_t flags
, ExecContext
*xc
) const
414 uint64_t *ipr
= xc
->regs
.ipr
;
416 // set fault address and flags
417 if (!xc
->misspeculating() && !xc
->regs
.intrlock
) {
418 // set VA register with faulting address
419 ipr
[AlphaISA::IPR_VA
] = vaddr
;
421 // set MM_STAT register flags
422 ipr
[AlphaISA::IPR_MM_STAT
] = (((xc
->regs
.opcode
& 0x3f) << 11)
423 | ((xc
->regs
.ra
& 0x1f) << 6)
426 // set VA_FORM register with faulting formatted address
427 ipr
[AlphaISA::IPR_VA_FORM
] =
428 ipr
[AlphaISA::IPR_MVPTBR
] | (VA_VPN(vaddr
) << 3);
430 // lock these registers until the VA register is read
431 xc
->regs
.intrlock
= true;
436 AlphaDtb::translate(MemReqPtr
&req
, bool write
) const
438 RegFile
*regs
= &req
->xc
->regs
;
440 InternalProcReg
*ipr
= regs
->ipr
;
447 AlphaISA::mode_type mode
=
448 (AlphaISA::mode_type
)DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]);
451 mode
= (req
->flags
& ALTMODE
) ?
452 (AlphaISA::mode_type
)ALT_MODE_AM(ipr
[AlphaISA::IPR_ALT_MODE
])
453 : AlphaISA::mode_kernel
;
456 // verify that this is a good virtual address
457 if (!validVirtualAddress(req
->vaddr
)) {
459 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_BAD_VA_MASK
|
463 if (write
) { write_acv
++; } else { read_acv
++; }
464 return Dtb_Fault_Fault
;
467 // Check for "superpage" mapping: when SP<1> is set, and
468 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
469 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) && VA_SPACE(req
->vaddr
) == 2) {
470 // only valid in kernel mode
471 if (DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]) != AlphaISA::mode_kernel
) {
473 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_ACV_MASK
),
475 if (write
) { write_acv
++; } else { read_acv
++; }
476 return Dtb_Acv_Fault
;
479 req
->flags
|= PHYSICAL
;
482 if (req
->flags
& PHYSICAL
) {
483 req
->paddr
= req
->vaddr
& PA_IMPL_MASK
;
485 // not a physical address: need to look up pte
487 AlphaISA::PTE
*pte
= lookup(VA_VPN(req
->vaddr
),
488 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
493 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_DTB_MISS_MASK
),
495 if (write
) { write_misses
++; } else { read_misses
++; }
496 return (req
->flags
& VPTE
) ? Pdtb_Miss_Fault
: Ndtb_Miss_Fault
;
499 req
->paddr
= PA_PFN2PA(pte
->ppn
) | VA_POFS(req
->vaddr
);
502 if (!(pte
->xwe
& MODE2MASK(mode
))) {
503 // declare the instruction access fault
504 fault(req
->vaddr
, MM_STAT_WR_MASK
| MM_STAT_ACV_MASK
|
505 (pte
->fonw
? MM_STAT_FONW_MASK
: 0),
508 return Dtb_Fault_Fault
;
511 fault(req
->vaddr
, MM_STAT_WR_MASK
| MM_STAT_FONW_MASK
,
514 return Dtb_Fault_Fault
;
517 if (!(pte
->xre
& MODE2MASK(mode
))) {
519 MM_STAT_ACV_MASK
| (pte
->fonr
? MM_STAT_FONR_MASK
: 0),
522 return Dtb_Acv_Fault
;
525 fault(req
->vaddr
, MM_STAT_FONR_MASK
, req
->xc
);
527 return Dtb_Fault_Fault
;
532 checkCacheability(req
);
545 AlphaISA::PTE
*pte
= &table
[nlu
];
551 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaItb
)
555 END_DECLARE_SIM_OBJECT_PARAMS(AlphaItb
)
557 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaItb
)
559 INIT_PARAM_DFLT(size
, "TLB size", 48)
561 END_INIT_SIM_OBJECT_PARAMS(AlphaItb
)
564 CREATE_SIM_OBJECT(AlphaItb
)
566 return new AlphaItb(getInstanceName(), size
);
569 REGISTER_SIM_OBJECT("AlphaITB", AlphaItb
)
571 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb
)
575 END_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb
)
577 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDtb
)
579 INIT_PARAM_DFLT(size
, "TLB size", 64)
581 END_INIT_SIM_OBJECT_PARAMS(AlphaDtb
)
584 CREATE_SIM_OBJECT(AlphaDtb
)
586 return new AlphaDtb(getInstanceName(), size
);
589 REGISTER_SIM_OBJECT("AlphaDTB", AlphaDtb
)