2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "base/inifile.hh"
34 #include "base/str.hh"
35 #include "base/trace.hh"
36 #include "cpu/exec_context.hh"
37 #include "sim/builder.hh"
38 #include "targetarch/alpha_memory.hh"
39 #include "targetarch/ev5.hh"
43 ///////////////////////////////////////////////////////////////////////
48 bool uncacheBit39
= false;
49 bool uncacheBit40
= false;
52 AlphaTLB::AlphaTLB(const string
&name
, int s
)
53 : SimObject(name
), size(s
), nlu(0)
55 table
= new AlphaISA::PTE
[size
];
56 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
65 // look up an entry in the TLB
67 AlphaTLB::lookup(Addr vpn
, uint8_t asn
) const
69 DPRINTF(TLB
, "lookup %#x\n", vpn
);
71 PageTable::const_iterator i
= lookupTable
.find(vpn
);
72 if (i
== lookupTable
.end())
75 while (i
->first
== vpn
) {
76 int index
= i
->second
;
77 AlphaISA::PTE
*pte
= &table
[index
];
79 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
))
91 AlphaTLB::checkCacheability(MemReqPtr
&req
)
93 // in Alpha, cacheability is controlled by upper-level bits of the
97 * We support having the uncacheable bit in either bit 39 or bit 40.
98 * The Turbolaser platform (and EV5) support having the bit in 39, but
99 * Tsunami (which Linux assumes uses an EV6) generates accesses with
100 * the bit in 40. So we must check for both, but we have debug flags
101 * to catch a weird case where both are used, which shouldn't happen.
104 if (req
->paddr
& PA_UNCACHED_BIT_40
||
105 req
->paddr
& PA_UNCACHED_BIT_39
) {
108 if (req
->paddr
& PA_UNCACHED_BIT_40
) {
110 panic("Bit 40 access follows bit 39 access, PA=%x\n",
114 } else if (req
->paddr
& PA_UNCACHED_BIT_39
) {
116 panic("Bit 39 acceess follows bit 40 access, PA=%x\n",
123 // IPR memory space not implemented
124 if (PA_IPR_SPACE(req
->paddr
))
125 if (!req
->xc
->misspeculating())
126 panic("IPR memory space not implemented! PA=%x\n",
129 // mark request as uncacheable
130 req
->flags
|= UNCACHEABLE
;
135 // insert a new TLB entry
137 AlphaTLB::insert(Addr vaddr
, AlphaISA::PTE
&pte
)
139 if (table
[nlu
].valid
) {
140 Addr oldvpn
= table
[nlu
].tag
;
141 PageTable::iterator i
= lookupTable
.find(oldvpn
);
143 if (i
== lookupTable
.end())
144 panic("TLB entry not found in lookupTable");
147 while ((index
= i
->second
) != nlu
) {
148 if (table
[index
].tag
!= oldvpn
)
149 panic("TLB entry not found in lookupTable");
154 DPRINTF(TLB
, "remove @%d: %#x -> %#x\n", nlu
, oldvpn
, table
[nlu
].ppn
);
156 lookupTable
.erase(i
);
159 Addr vpn
= VA_VPN(vaddr
);
160 DPRINTF(TLB
, "insert @%d: %#x -> %#x\n", nlu
, vpn
, pte
.ppn
);
163 table
[nlu
].tag
= vpn
;
164 table
[nlu
].valid
= true;
166 lookupTable
.insert(make_pair(vpn
, nlu
));
173 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
179 AlphaTLB::flushProcesses()
181 PageTable::iterator i
= lookupTable
.begin();
182 PageTable::iterator end
= lookupTable
.end();
184 int index
= i
->second
;
185 AlphaISA::PTE
*pte
= &table
[index
];
189 DPRINTF(TLB
, "flush @%d: %#x -> %#x\n", index
, pte
->tag
, pte
->ppn
);
191 lookupTable
.erase(i
);
199 AlphaTLB::flushAddr(Addr vaddr
, uint8_t asn
)
201 Addr vpn
= VA_VPN(vaddr
);
203 PageTable::iterator i
= lookupTable
.find(vpn
);
204 if (i
== lookupTable
.end())
207 while (i
->first
== vpn
) {
208 int index
= i
->second
;
209 AlphaISA::PTE
*pte
= &table
[index
];
212 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
)) {
213 DPRINTF(TLB
, "flushaddr @%d: %#x -> %#x\n", index
, vpn
, pte
->ppn
);
215 // invalidate this entry
218 lookupTable
.erase(i
);
227 AlphaTLB::serialize(ostream
&os
)
229 SERIALIZE_SCALAR(size
);
230 SERIALIZE_SCALAR(nlu
);
232 for (int i
= 0; i
< size
; i
++) {
233 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
234 table
[i
].serialize(os
);
239 AlphaTLB::unserialize(Checkpoint
*cp
, const string
§ion
)
241 UNSERIALIZE_SCALAR(size
);
242 UNSERIALIZE_SCALAR(nlu
);
244 for (int i
= 0; i
< size
; i
++) {
245 table
[i
].unserialize(cp
, csprintf("%s.PTE%d", section
, i
));
246 if (table
[i
].valid
) {
247 lookupTable
.insert(make_pair(table
[i
].tag
, i
));
253 ///////////////////////////////////////////////////////////////////////
257 AlphaITB::AlphaITB(const std::string
&name
, int size
)
258 : AlphaTLB(name
, size
)
266 .name(name() + ".hits")
269 .name(name() + ".misses")
272 .name(name() + ".acv")
275 .name(name() + ".accesses")
276 .desc("ITB accesses");
278 accesses
= hits
+ misses
;
282 AlphaITB::fault(Addr pc
, ExecContext
*xc
) const
284 uint64_t *ipr
= xc
->regs
.ipr
;
286 if (!xc
->misspeculating()) {
287 ipr
[AlphaISA::IPR_ITB_TAG
] = pc
;
288 ipr
[AlphaISA::IPR_IFAULT_VA_FORM
] =
289 ipr
[AlphaISA::IPR_IVPTBR
] | (VA_VPN(pc
) << 3);
295 AlphaITB::translate(MemReqPtr
&req
) const
297 InternalProcReg
*ipr
= req
->xc
->regs
.ipr
;
299 if (PC_PAL(req
->vaddr
)) {
300 // strip off PAL PC marker (lsb is 1)
301 req
->paddr
= (req
->vaddr
& ~3) & PA_IMPL_MASK
;
306 if (req
->flags
& PHYSICAL
) {
307 req
->paddr
= req
->vaddr
;
309 // verify that this is a good virtual address
310 if (!validVirtualAddress(req
->vaddr
)) {
311 fault(req
->vaddr
, req
->xc
);
313 return ITB_Acv_Fault
;
316 // Check for "superpage" mapping: when SP<1> is set, and
317 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
318 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) &&
319 VA_SPACE(req
->vaddr
) == 2) {
321 // only valid in kernel mode
322 if (ICM_CM(ipr
[AlphaISA::IPR_ICM
]) != AlphaISA::mode_kernel
) {
323 fault(req
->vaddr
, req
->xc
);
325 return ITB_Acv_Fault
;
328 req
->paddr
= req
->vaddr
& PA_IMPL_MASK
;
330 // sign extend the physical address properly
331 if (req
->paddr
& PA_UNCACHED_BIT_39
||
332 req
->paddr
& PA_UNCACHED_BIT_40
)
333 req
->paddr
|= 0xf0000000000ULL
;
335 req
->paddr
&= 0xffffffffffULL
;
338 // not a physical address: need to look up pte
339 AlphaISA::PTE
*pte
= lookup(VA_VPN(req
->vaddr
),
340 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
343 fault(req
->vaddr
, req
->xc
);
345 return ITB_Fault_Fault
;
348 req
->paddr
= PA_PFN2PA(pte
->ppn
) + VA_POFS(req
->vaddr
& ~3);
350 // check permissions for this access
351 if (!(pte
->xre
& (1 << ICM_CM(ipr
[AlphaISA::IPR_ICM
])))) {
352 // instruction access fault
353 fault(req
->vaddr
, req
->xc
);
355 return ITB_Acv_Fault
;
362 // check that the physical address is ok (catch bad physical addresses)
363 if (req
->paddr
& ~PA_IMPL_MASK
)
364 return Machine_Check_Fault
;
366 checkCacheability(req
);
371 ///////////////////////////////////////////////////////////////////////
375 AlphaDTB::AlphaDTB(const std::string
&name
, int size
)
376 : AlphaTLB(name
, size
)
383 .name(name() + ".read_hits")
384 .desc("DTB read hits")
388 .name(name() + ".read_misses")
389 .desc("DTB read misses")
393 .name(name() + ".read_acv")
394 .desc("DTB read access violations")
398 .name(name() + ".read_accesses")
399 .desc("DTB read accesses")
403 .name(name() + ".write_hits")
404 .desc("DTB write hits")
408 .name(name() + ".write_misses")
409 .desc("DTB write misses")
413 .name(name() + ".write_acv")
414 .desc("DTB write access violations")
418 .name(name() + ".write_accesses")
419 .desc("DTB write accesses")
423 .name(name() + ".hits")
428 .name(name() + ".misses")
433 .name(name() + ".acv")
434 .desc("DTB access violations")
438 .name(name() + ".accesses")
439 .desc("DTB accesses")
442 hits
= read_hits
+ write_hits
;
443 misses
= read_misses
+ write_misses
;
444 acv
= read_acv
+ write_acv
;
445 accesses
= read_accesses
+ write_accesses
;
449 AlphaDTB::fault(Addr vaddr
, uint64_t flags
, ExecContext
*xc
) const
451 uint64_t *ipr
= xc
->regs
.ipr
;
453 // set fault address and flags
454 if (!xc
->misspeculating() && !xc
->regs
.intrlock
) {
455 // set VA register with faulting address
456 ipr
[AlphaISA::IPR_VA
] = vaddr
;
458 // set MM_STAT register flags
459 ipr
[AlphaISA::IPR_MM_STAT
] = (((xc
->regs
.opcode
& 0x3f) << 11)
460 | ((xc
->regs
.ra
& 0x1f) << 6)
463 // set VA_FORM register with faulting formatted address
464 ipr
[AlphaISA::IPR_VA_FORM
] =
465 ipr
[AlphaISA::IPR_MVPTBR
] | (VA_VPN(vaddr
) << 3);
467 // lock these registers until the VA register is read
468 xc
->regs
.intrlock
= true;
473 AlphaDTB::translate(MemReqPtr
&req
, bool write
) const
475 RegFile
*regs
= &req
->xc
->regs
;
477 InternalProcReg
*ipr
= regs
->ipr
;
479 AlphaISA::mode_type mode
=
480 (AlphaISA::mode_type
)DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]);
483 mode
= (req
->flags
& ALTMODE
) ?
484 (AlphaISA::mode_type
)ALT_MODE_AM(ipr
[AlphaISA::IPR_ALT_MODE
])
485 : AlphaISA::mode_kernel
;
488 if (req
->flags
& PHYSICAL
) {
489 req
->paddr
= req
->vaddr
;
491 // verify that this is a good virtual address
492 if (!validVirtualAddress(req
->vaddr
)) {
494 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_BAD_VA_MASK
|
498 if (write
) { write_acv
++; } else { read_acv
++; }
499 return DTB_Fault_Fault
;
502 // Check for "superpage" mapping: when SP<1> is set, and
503 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
504 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) &&
505 VA_SPACE(req
->vaddr
) == 2) {
507 // only valid in kernel mode
508 if (DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]) !=
509 AlphaISA::mode_kernel
) {
511 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_ACV_MASK
),
513 if (write
) { write_acv
++; } else { read_acv
++; }
514 return DTB_Acv_Fault
;
517 req
->paddr
= req
->vaddr
& PA_IMPL_MASK
;
519 // sign extend the physical address properly
520 if (req
->paddr
& PA_UNCACHED_BIT_39
||
521 req
->paddr
& PA_UNCACHED_BIT_40
)
522 req
->paddr
|= 0xf0000000000ULL
;
524 req
->paddr
&= 0xffffffffffULL
;
532 // not a physical address: need to look up pte
533 AlphaISA::PTE
*pte
= lookup(VA_VPN(req
->vaddr
),
534 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
539 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_DTB_MISS_MASK
),
541 if (write
) { write_misses
++; } else { read_misses
++; }
542 return (req
->flags
& VPTE
) ? Pdtb_Miss_Fault
: Ndtb_Miss_Fault
;
545 req
->paddr
= PA_PFN2PA(pte
->ppn
) | VA_POFS(req
->vaddr
);
548 if (!(pte
->xwe
& MODE2MASK(mode
))) {
549 // declare the instruction access fault
550 fault(req
->vaddr
, MM_STAT_WR_MASK
| MM_STAT_ACV_MASK
|
551 (pte
->fonw
? MM_STAT_FONW_MASK
: 0),
554 return DTB_Fault_Fault
;
557 fault(req
->vaddr
, MM_STAT_WR_MASK
| MM_STAT_FONW_MASK
,
560 return DTB_Fault_Fault
;
563 if (!(pte
->xre
& MODE2MASK(mode
))) {
566 (pte
->fonr
? MM_STAT_FONR_MASK
: 0),
569 return DTB_Acv_Fault
;
572 fault(req
->vaddr
, MM_STAT_FONR_MASK
, req
->xc
);
574 return DTB_Fault_Fault
;
585 // check that the physical address is ok (catch bad physical addresses)
586 if (req
->paddr
& ~PA_IMPL_MASK
)
587 return Machine_Check_Fault
;
589 checkCacheability(req
);
595 AlphaTLB::index(bool advance
)
597 AlphaISA::PTE
*pte
= &table
[nlu
];
605 DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB
)
607 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB
)
611 END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB
)
613 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB
)
615 INIT_PARAM_DFLT(size
, "TLB size", 48)
617 END_INIT_SIM_OBJECT_PARAMS(AlphaITB
)
620 CREATE_SIM_OBJECT(AlphaITB
)
622 return new AlphaITB(getInstanceName(), size
);
625 REGISTER_SIM_OBJECT("AlphaITB", AlphaITB
)
627 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB
)
631 END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB
)
633 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB
)
635 INIT_PARAM_DFLT(size
, "TLB size", 64)
637 END_INIT_SIM_OBJECT_PARAMS(AlphaDTB
)
640 CREATE_SIM_OBJECT(AlphaDTB
)
642 return new AlphaDTB(getInstanceName(), size
);
645 REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB
)