2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "base/inifile.hh"
34 #include "base/str.hh"
35 #include "base/trace.hh"
36 #include "cpu/exec_context.hh"
37 #include "sim/builder.hh"
38 #include "targetarch/alpha_memory.hh"
39 #include "targetarch/ev5.hh"
43 ///////////////////////////////////////////////////////////////////////
47 AlphaTlb::AlphaTlb(const string
&name
, int s
)
48 : SimObject(name
), size(s
), nlu(0)
50 table
= new AlphaISA::PTE
[size
];
51 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
60 // look up an entry in the TLB
62 AlphaTlb::lookup(Addr vpn
, uint8_t asn
) const
64 DPRINTF(TLB
, "lookup %#x\n", vpn
);
66 PageTable::const_iterator i
= lookupTable
.find(vpn
);
67 if (i
== lookupTable
.end())
70 while (i
->first
== vpn
) {
71 int index
= i
->second
;
72 AlphaISA::PTE
*pte
= &table
[index
];
74 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
))
86 AlphaTlb::checkCacheability(MemReqPtr req
)
88 // in Alpha, cacheability is controlled by upper-level bits of the
90 if (req
->paddr
& PA_UNCACHED_BIT
) {
91 if (PA_IPR_SPACE(req
->paddr
)) {
92 // IPR memory space not implemented
93 if (!req
->xc
->misspeculating())
94 panic("IPR memory space not implemented! PA=%x\n", req
->paddr
);
96 // mark request as uncacheable
97 req
->flags
|= UNCACHEABLE
;
103 // insert a new TLB entry
105 AlphaTlb::insert(Addr vaddr
, AlphaISA::PTE
&pte
)
107 if (table
[nlu
].valid
) {
108 Addr oldvpn
= table
[nlu
].tag
;
109 PageTable::iterator i
= lookupTable
.find(oldvpn
);
111 if (i
== lookupTable
.end())
112 panic("TLB entry not found in lookupTable");
115 while ((index
= i
->second
) != nlu
) {
116 if (table
[index
].tag
!= oldvpn
)
117 panic("TLB entry not found in lookupTable");
122 DPRINTF(TLB
, "remove @%d: %#x -> %#x\n", nlu
, oldvpn
, table
[nlu
].ppn
);
124 lookupTable
.erase(i
);
127 Addr vpn
= VA_VPN(vaddr
);
128 DPRINTF(TLB
, "insert @%d: %#x -> %#x\n", nlu
, vpn
, pte
.ppn
);
131 table
[nlu
].tag
= vpn
;
132 table
[nlu
].valid
= true;
134 lookupTable
.insert(make_pair(vpn
, nlu
));
141 memset(table
, 0, sizeof(AlphaISA::PTE
[size
]));
147 AlphaTlb::flushProcesses()
149 PageTable::iterator i
= lookupTable
.begin();
150 PageTable::iterator end
= lookupTable
.end();
152 int index
= i
->second
;
153 AlphaISA::PTE
*pte
= &table
[index
];
157 DPRINTF(TLB
, "flush @%d: %#x -> %#x\n", index
, pte
->tag
, pte
->ppn
);
159 lookupTable
.erase(i
);
167 AlphaTlb::flushAddr(Addr vaddr
, uint8_t asn
)
169 Addr vpn
= VA_VPN(vaddr
);
171 PageTable::iterator i
= lookupTable
.find(vpn
);
172 if (i
== lookupTable
.end())
175 while (i
->first
== vpn
) {
176 int index
= i
->second
;
177 AlphaISA::PTE
*pte
= &table
[index
];
180 if (vpn
== pte
->tag
&& (pte
->asma
|| pte
->asn
== asn
)) {
181 DPRINTF(TLB
, "flushaddr @%d: %#x -> %#x\n", index
, vpn
, pte
->ppn
);
183 // invalidate this entry
186 lookupTable
.erase(i
);
195 AlphaTlb::serialize(ostream
&os
)
197 SERIALIZE_SCALAR(size
);
198 SERIALIZE_SCALAR(nlu
);
200 for (int i
= 0; i
< size
; i
++) {
201 nameOut(os
, csprintf("%s.PTE%d", name(), i
));
202 table
[i
].serialize(os
);
207 AlphaTlb::unserialize(const IniFile
*db
, const string
§ion
)
209 UNSERIALIZE_SCALAR(size
);
210 UNSERIALIZE_SCALAR(nlu
);
212 for (int i
= 0; i
< size
; i
++) {
213 table
[i
].unserialize(db
, csprintf("%s.PTE%d", section
, i
));
214 if (table
[i
].valid
) {
215 lookupTable
.insert(make_pair(table
[i
].tag
, i
));
221 ///////////////////////////////////////////////////////////////////////
225 AlphaItb::AlphaItb(const std::string
&name
, int size
)
226 : AlphaTlb(name
, size
)
234 .name(name() + ".hits")
237 .name(name() + ".misses")
240 .name(name() + ".acv")
243 .name(name() + ".accesses")
244 .desc("ITB accesses");
246 accesses
= hits
+ misses
;
250 AlphaItb::fault(Addr pc
, ExecContext
*xc
) const
252 uint64_t *ipr
= xc
->regs
.ipr
;
254 if (!xc
->misspeculating()) {
255 ipr
[AlphaISA::IPR_ITB_TAG
] = pc
;
256 ipr
[AlphaISA::IPR_IFAULT_VA_FORM
] =
257 ipr
[AlphaISA::IPR_IVPTBR
] | (VA_VPN(pc
) << 3);
263 AlphaItb::translate(MemReqPtr req
) const
265 InternalProcReg
*ipr
= req
->xc
->regs
.ipr
;
267 if (PC_PAL(req
->vaddr
)) {
268 // strip off PAL PC marker (lsb is 1)
269 req
->paddr
= (req
->vaddr
& ~3) & PA_IMPL_MASK
;
274 // verify that this is a good virtual address
275 if (!validVirtualAddress(req
->vaddr
)) {
276 fault(req
->vaddr
, req
->xc
);
278 return Itb_Acv_Fault
;
281 // Check for "superpage" mapping: when SP<1> is set, and
282 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
283 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) &&
284 VA_SPACE(req
->vaddr
) == 2) {
285 // only valid in kernel mode
286 if (ICM_CM(ipr
[AlphaISA::IPR_ICM
]) != AlphaISA::mode_kernel
) {
287 fault(req
->vaddr
, req
->xc
);
289 return Itb_Acv_Fault
;
292 req
->flags
|= PHYSICAL
;
295 if (req
->flags
& PHYSICAL
) {
296 req
->paddr
= req
->vaddr
& PA_IMPL_MASK
;
298 // not a physical address: need to look up pte
300 AlphaISA::PTE
*pte
= lookup(VA_VPN(req
->vaddr
),
301 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
304 fault(req
->vaddr
, req
->xc
);
306 return Itb_Fault_Fault
;
309 req
->paddr
= PA_PFN2PA(pte
->ppn
) + VA_POFS(req
->vaddr
& ~3);
311 // check permissions for this access
312 if (!(pte
->xre
& (1 << ICM_CM(ipr
[AlphaISA::IPR_ICM
])))) {
313 // instruction access fault
314 fault(req
->vaddr
, req
->xc
);
316 return Itb_Acv_Fault
;
320 checkCacheability(req
);
326 ///////////////////////////////////////////////////////////////////////
330 AlphaDtb::AlphaDtb(const std::string
&name
, int size
)
331 : AlphaTlb(name
, size
)
338 .name(name() + ".read_hits")
339 .desc("DTB read hits")
343 .name(name() + ".read_misses")
344 .desc("DTB read misses")
348 .name(name() + ".read_acv")
349 .desc("DTB read access violations")
353 .name(name() + ".read_accesses")
354 .desc("DTB read accesses")
358 .name(name() + ".write_hits")
359 .desc("DTB write hits")
363 .name(name() + ".write_misses")
364 .desc("DTB write misses")
368 .name(name() + ".write_acv")
369 .desc("DTB write access violations")
373 .name(name() + ".write_accesses")
374 .desc("DTB write accesses")
378 .name(name() + ".hits")
383 .name(name() + ".misses")
388 .name(name() + ".acv")
389 .desc("DTB access violations")
393 .name(name() + ".accesses")
394 .desc("DTB accesses")
397 hits
= read_hits
+ write_hits
;
398 misses
= read_misses
+ write_misses
;
399 acv
= read_acv
+ write_acv
;
400 accesses
= read_accesses
+ write_accesses
;
404 AlphaDtb::fault(Addr vaddr
, uint64_t flags
, ExecContext
*xc
) const
406 uint64_t *ipr
= xc
->regs
.ipr
;
408 // set fault address and flags
409 if (!xc
->misspeculating() && !xc
->regs
.intrlock
) {
410 // set VA register with faulting address
411 ipr
[AlphaISA::IPR_VA
] = vaddr
;
413 // set MM_STAT register flags
414 ipr
[AlphaISA::IPR_MM_STAT
] = (((xc
->regs
.opcode
& 0x3f) << 11)
415 | ((xc
->regs
.ra
& 0x1f) << 6)
418 // set VA_FORM register with faulting formatted address
419 ipr
[AlphaISA::IPR_VA_FORM
] =
420 ipr
[AlphaISA::IPR_MVPTBR
] | (VA_VPN(vaddr
) << 3);
422 // lock these registers until the VA register is read
423 xc
->regs
.intrlock
= true;
428 AlphaDtb::translate(MemReqPtr req
, bool write
) const
430 RegFile
*regs
= &req
->xc
->regs
;
432 InternalProcReg
*ipr
= regs
->ipr
;
439 AlphaISA::md_mode_type mode
=
440 (AlphaISA::md_mode_type
)DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]);
443 mode
= (req
->flags
& ALTMODE
) ? (AlphaISA::md_mode_type
)
444 (ALT_MODE_AM(ipr
[AlphaISA::IPR_ALT_MODE
]))
445 : AlphaISA::mode_kernel
;
448 // verify that this is a good virtual address
449 if (!validVirtualAddress(req
->vaddr
)) {
451 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_BAD_VA_MASK
|
455 if (write
) { write_acv
++; } else { read_acv
++; }
456 return Dtb_Fault_Fault
;
459 // Check for "superpage" mapping: when SP<1> is set, and
460 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
461 if ((MCSR_SP(ipr
[AlphaISA::IPR_MCSR
]) & 2) && VA_SPACE(req
->vaddr
) == 2) {
462 // only valid in kernel mode
463 if (DTB_CM_CM(ipr
[AlphaISA::IPR_DTB_CM
]) != AlphaISA::mode_kernel
) {
465 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_ACV_MASK
),
467 if (write
) { write_acv
++; } else { read_acv
++; }
468 return Dtb_Acv_Fault
;
471 req
->flags
|= PHYSICAL
;
474 if (req
->flags
& PHYSICAL
) {
475 req
->paddr
= req
->vaddr
& PA_IMPL_MASK
;
477 // not a physical address: need to look up pte
479 AlphaISA::PTE
*pte
= lookup(VA_VPN(req
->vaddr
),
480 DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
485 ((write
? MM_STAT_WR_MASK
: 0) | MM_STAT_DTB_MISS_MASK
),
487 if (write
) { write_misses
++; } else { read_misses
++; }
488 return (req
->flags
& VPTE
) ? Pdtb_Miss_Fault
: Ndtb_Miss_Fault
;
491 req
->paddr
= PA_PFN2PA(pte
->ppn
) | VA_POFS(req
->vaddr
);
494 if (!(pte
->xwe
& MODE2MASK(mode
))) {
495 // declare the instruction access fault
496 fault(req
->vaddr
, MM_STAT_WR_MASK
| MM_STAT_ACV_MASK
|
497 (pte
->fonw
? MM_STAT_FONW_MASK
: 0),
500 return Dtb_Fault_Fault
;
503 fault(req
->vaddr
, MM_STAT_WR_MASK
| MM_STAT_FONW_MASK
,
506 return Dtb_Fault_Fault
;
509 if (!(pte
->xre
& MODE2MASK(mode
))) {
511 MM_STAT_ACV_MASK
| (pte
->fonr
? MM_STAT_FONR_MASK
: 0),
514 return Dtb_Acv_Fault
;
517 fault(req
->vaddr
, MM_STAT_FONR_MASK
, req
->xc
);
519 return Dtb_Fault_Fault
;
524 checkCacheability(req
);
537 AlphaISA::PTE
*pte
= &table
[nlu
];
543 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaItb
)
547 END_DECLARE_SIM_OBJECT_PARAMS(AlphaItb
)
549 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaItb
)
551 INIT_PARAM_DFLT(size
, "TLB size", 48)
553 END_INIT_SIM_OBJECT_PARAMS(AlphaItb
)
556 CREATE_SIM_OBJECT(AlphaItb
)
558 return new AlphaItb(getInstanceName(), size
);
561 REGISTER_SIM_OBJECT("AlphaITB", AlphaItb
)
563 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb
)
567 END_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb
)
569 BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDtb
)
571 INIT_PARAM_DFLT(size
, "TLB size", 64)
573 END_INIT_SIM_OBJECT_PARAMS(AlphaDtb
)
576 CREATE_SIM_OBJECT(AlphaDtb
)
578 return new AlphaDtb(getInstanceName(), size
);
581 REGISTER_SIM_OBJECT("AlphaDTB", AlphaDtb
)