3 #include "arch/alpha/alpha_memory.hh"
4 #include "arch/alpha/isa_traits.hh"
5 #include "arch/alpha/osfpal.hh"
7 #include "base/remote_gdb.hh"
8 #include "base/stats/events.hh"
9 #include "cpu/base_cpu.hh"
10 #include "cpu/exec_context.hh"
11 #include "cpu/fast_cpu/fast_cpu.hh"
12 #include "kern/kernel_stats.hh"
13 #include "sim/debug.hh"
14 #include "sim/sim_events.hh"
19 #error This code is only valid for EV5 systems
22 ////////////////////////////////////////////////////////////////////////
27 AlphaISA::swap_palshadow(RegFile
*regs
, bool use_shadow
)
29 if (regs
->pal_shadow
== use_shadow
)
30 panic("swap_palshadow: wrong PAL shadow state");
32 regs
->pal_shadow
= use_shadow
;
34 for (int i
= 0; i
< NumIntRegs
; i
++) {
36 IntReg temp
= regs
->intRegFile
[i
];
37 regs
->intRegFile
[i
] = regs
->palregs
[i
];
38 regs
->palregs
[i
] = temp
;
43 ////////////////////////////////////////////////////////////////////////
45 // Machine dependent functions
48 AlphaISA::initCPU(RegFile
*regs
)
51 // CPU comes up with PAL regs enabled
52 swap_palshadow(regs
, true);
54 regs
->pc
= regs
->ipr
[IPR_PAL_BASE
] + fault_addr
[Reset_Fault
];
55 regs
->npc
= regs
->pc
+ sizeof(MachInst
);
58 ////////////////////////////////////////////////////////////////////////
60 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
63 AlphaISA::fault_addr
[Num_Faults
] = {
64 0x0000, /* No_Fault */
65 0x0001, /* Reset_Fault */
66 0x0401, /* Machine_Check_Fault */
67 0x0501, /* Arithmetic_Fault */
68 0x0101, /* Interrupt_Fault */
69 0x0201, /* Ndtb_Miss_Fault */
70 0x0281, /* Pdtb_Miss_Fault */
71 0x0301, /* Alignment_Fault */
72 0x0381, /* DTB_Fault_Fault */
73 0x0381, /* DTB_Acv_Fault */
74 0x0181, /* ITB_Miss_Fault */
75 0x0181, /* ITB_Fault_Fault */
76 0x0081, /* ITB_Acv_Fault */
77 0x0481, /* Unimplemented_Opcode_Fault */
78 0x0581, /* Fen_Fault */
79 0x2001, /* Pal_Fault */
80 0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
83 const int AlphaISA::reg_redir
[AlphaISA::NumIntRegs
] = {
84 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
85 /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
86 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
87 /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
89 ////////////////////////////////////////////////////////////////////////
94 AlphaISA::initIPRs(RegFile
*regs
)
96 uint64_t *ipr
= regs
->ipr
;
98 bzero((char *)ipr
, NumInternalProcRegs
* sizeof(InternalProcReg
));
99 ipr
[IPR_PAL_BASE
] = PAL_BASE
;
106 AlphaISA::processInterrupts(XC
*xc
)
108 //Check if there are any outstanding interrupts
109 //Handle the interrupts
112 IntReg
*ipr
= xc
->getIprPtr();
114 check_interrupts
= 0;
117 panic("asynchronous traps not implemented\n");
120 for (int i
= INTLEVEL_SOFTWARE_MIN
;
121 i
< INTLEVEL_SOFTWARE_MAX
; i
++) {
122 if (ipr
[IPR_SIRR
] & (ULL(1) << i
)) {
123 // See table 4-19 of the 21164 hardware reference
124 ipl
= (i
- INTLEVEL_SOFTWARE_MIN
) + 1;
125 summary
|= (ULL(1) << i
);
130 uint64_t interrupts
= xc
->intr_status();
133 for (int i
= INTLEVEL_EXTERNAL_MIN
;
134 i
< INTLEVEL_EXTERNAL_MAX
; i
++) {
135 if (interrupts
& (ULL(1) << i
)) {
136 // See table 4-19 of the 21164 hardware reference
138 summary
|= (ULL(1) << i
);
143 if (ipl
&& ipl
> ipr
[IPR_IPLR
]) {
144 ipr
[IPR_ISR
] = summary
;
145 ipr
[IPR_INTID
] = ipl
;
146 xc
->trap(Interrupt_Fault
);
147 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
148 ipr
[IPR_IPLR
], ipl
, summary
);
155 AlphaISA::zeroRegisters(XC
*xc
)
157 // Insure ISA semantics
158 // (no longer very clean due to the change in setIntReg() in the
159 // cpu model. Consider changing later.)
160 xc
->xc
->setIntReg(ZeroReg
, 0);
161 xc
->xc
->setFloatRegDouble(ZeroReg
, 0.0);
165 ExecContext::ev5_trap(Fault fault
)
167 DPRINTF(Fault
, "Fault %s at PC: %#x\n", FaultName(fault
), regs
.pc
);
168 cpu
->recordEvent(csprintf("Fault %s", FaultName(fault
)));
170 assert(!misspeculating());
171 kernelStats
->fault(fault
);
173 if (fault
== Arithmetic_Fault
)
174 panic("Arithmetic traps are unimplemented!");
176 AlphaISA::InternalProcReg
*ipr
= regs
.ipr
;
178 // exception restart address
179 if (fault
!= Interrupt_Fault
|| !PC_PAL(regs
.pc
))
180 ipr
[AlphaISA::IPR_EXC_ADDR
] = regs
.pc
;
182 if (fault
== Pal_Fault
|| fault
== Arithmetic_Fault
/* ||
183 fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
184 // traps... skip faulting instruction
185 ipr
[AlphaISA::IPR_EXC_ADDR
] += 4;
188 if (!PC_PAL(regs
.pc
))
189 AlphaISA::swap_palshadow(®s
, true);
191 regs
.pc
= ipr
[AlphaISA::IPR_PAL_BASE
] + AlphaISA::fault_addr
[fault
];
192 regs
.npc
= regs
.pc
+ sizeof(MachInst
);
197 AlphaISA::intr_post(RegFile
*regs
, Fault fault
, Addr pc
)
199 InternalProcReg
*ipr
= regs
->ipr
;
200 bool use_pc
= (fault
== No_Fault
);
202 if (fault
== Arithmetic_Fault
)
203 panic("arithmetic faults NYI...");
205 // compute exception restart address
206 if (use_pc
|| fault
== Pal_Fault
|| fault
== Arithmetic_Fault
) {
207 // traps... skip faulting instruction
208 ipr
[IPR_EXC_ADDR
] = regs
->pc
+ 4;
210 // fault, post fault at excepting instruction
211 ipr
[IPR_EXC_ADDR
] = regs
->pc
;
214 // jump to expection address (PAL PC bit set here as well...)
216 regs
->npc
= ipr
[IPR_PAL_BASE
] + fault_addr
[fault
];
218 regs
->npc
= ipr
[IPR_PAL_BASE
] + pc
;
220 // that's it! (orders of magnitude less painful than x86)
223 bool AlphaISA::check_interrupts
= false;
228 uint64_t *ipr
= regs
.ipr
;
230 if (!PC_PAL(regs
.pc
))
231 return Unimplemented_Opcode_Fault
;
233 setNextPC(ipr
[AlphaISA::IPR_EXC_ADDR
]);
235 if (!misspeculating()) {
236 kernelStats
->hwrei();
238 if ((ipr
[AlphaISA::IPR_EXC_ADDR
] & 1) == 0)
239 AlphaISA::swap_palshadow(®s
, false);
241 AlphaISA::check_interrupts
= true;
244 // FIXME: XXX check for interrupts? XXX
249 ExecContext::readIpr(int idx
, Fault
&fault
)
251 uint64_t *ipr
= regs
.ipr
;
252 uint64_t retval
= 0; // return value, default 0
255 case AlphaISA::IPR_PALtemp0
:
256 case AlphaISA::IPR_PALtemp1
:
257 case AlphaISA::IPR_PALtemp2
:
258 case AlphaISA::IPR_PALtemp3
:
259 case AlphaISA::IPR_PALtemp4
:
260 case AlphaISA::IPR_PALtemp5
:
261 case AlphaISA::IPR_PALtemp6
:
262 case AlphaISA::IPR_PALtemp7
:
263 case AlphaISA::IPR_PALtemp8
:
264 case AlphaISA::IPR_PALtemp9
:
265 case AlphaISA::IPR_PALtemp10
:
266 case AlphaISA::IPR_PALtemp11
:
267 case AlphaISA::IPR_PALtemp12
:
268 case AlphaISA::IPR_PALtemp13
:
269 case AlphaISA::IPR_PALtemp14
:
270 case AlphaISA::IPR_PALtemp15
:
271 case AlphaISA::IPR_PALtemp16
:
272 case AlphaISA::IPR_PALtemp17
:
273 case AlphaISA::IPR_PALtemp18
:
274 case AlphaISA::IPR_PALtemp19
:
275 case AlphaISA::IPR_PALtemp20
:
276 case AlphaISA::IPR_PALtemp21
:
277 case AlphaISA::IPR_PALtemp22
:
278 case AlphaISA::IPR_PALtemp23
:
279 case AlphaISA::IPR_PAL_BASE
:
281 case AlphaISA::IPR_IVPTBR
:
282 case AlphaISA::IPR_DC_MODE
:
283 case AlphaISA::IPR_MAF_MODE
:
284 case AlphaISA::IPR_ISR
:
285 case AlphaISA::IPR_EXC_ADDR
:
286 case AlphaISA::IPR_IC_PERR_STAT
:
287 case AlphaISA::IPR_DC_PERR_STAT
:
288 case AlphaISA::IPR_MCSR
:
289 case AlphaISA::IPR_ASTRR
:
290 case AlphaISA::IPR_ASTER
:
291 case AlphaISA::IPR_SIRR
:
292 case AlphaISA::IPR_ICSR
:
293 case AlphaISA::IPR_ICM
:
294 case AlphaISA::IPR_DTB_CM
:
295 case AlphaISA::IPR_IPLR
:
296 case AlphaISA::IPR_INTID
:
297 case AlphaISA::IPR_PMCTR
:
302 case AlphaISA::IPR_CC
:
303 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
304 retval
|= curTick
& ULL(0x00000000ffffffff);
307 case AlphaISA::IPR_VA
:
311 case AlphaISA::IPR_VA_FORM
:
312 case AlphaISA::IPR_MM_STAT
:
313 case AlphaISA::IPR_IFAULT_VA_FORM
:
314 case AlphaISA::IPR_EXC_MASK
:
315 case AlphaISA::IPR_EXC_SUM
:
319 case AlphaISA::IPR_DTB_PTE
:
321 AlphaISA::PTE
&pte
= dtb
->index(!misspeculating());
323 retval
|= ((u_int64_t
)pte
.ppn
& ULL(0x7ffffff)) << 32;
324 retval
|= ((u_int64_t
)pte
.xre
& ULL(0xf)) << 8;
325 retval
|= ((u_int64_t
)pte
.xwe
& ULL(0xf)) << 12;
326 retval
|= ((u_int64_t
)pte
.fonr
& ULL(0x1)) << 1;
327 retval
|= ((u_int64_t
)pte
.fonw
& ULL(0x1))<< 2;
328 retval
|= ((u_int64_t
)pte
.asma
& ULL(0x1)) << 4;
329 retval
|= ((u_int64_t
)pte
.asn
& ULL(0x7f)) << 57;
333 // write only registers
334 case AlphaISA::IPR_HWINT_CLR
:
335 case AlphaISA::IPR_SL_XMIT
:
336 case AlphaISA::IPR_DC_FLUSH
:
337 case AlphaISA::IPR_IC_FLUSH
:
338 case AlphaISA::IPR_ALT_MODE
:
339 case AlphaISA::IPR_DTB_IA
:
340 case AlphaISA::IPR_DTB_IAP
:
341 case AlphaISA::IPR_ITB_IA
:
342 case AlphaISA::IPR_ITB_IAP
:
343 fault
= Unimplemented_Opcode_Fault
;
348 fault
= Unimplemented_Opcode_Fault
;
356 // Cause the simulator to break when changing to the following IPL
361 ExecContext::setIpr(int idx
, uint64_t val
)
363 uint64_t *ipr
= regs
.ipr
;
366 if (misspeculating())
370 case AlphaISA::IPR_PALtemp0
:
371 case AlphaISA::IPR_PALtemp1
:
372 case AlphaISA::IPR_PALtemp2
:
373 case AlphaISA::IPR_PALtemp3
:
374 case AlphaISA::IPR_PALtemp4
:
375 case AlphaISA::IPR_PALtemp5
:
376 case AlphaISA::IPR_PALtemp6
:
377 case AlphaISA::IPR_PALtemp7
:
378 case AlphaISA::IPR_PALtemp8
:
379 case AlphaISA::IPR_PALtemp9
:
380 case AlphaISA::IPR_PALtemp10
:
381 case AlphaISA::IPR_PALtemp11
:
382 case AlphaISA::IPR_PALtemp12
:
383 case AlphaISA::IPR_PALtemp13
:
384 case AlphaISA::IPR_PALtemp14
:
385 case AlphaISA::IPR_PALtemp15
:
386 case AlphaISA::IPR_PALtemp16
:
387 case AlphaISA::IPR_PALtemp17
:
388 case AlphaISA::IPR_PALtemp18
:
389 case AlphaISA::IPR_PALtemp19
:
390 case AlphaISA::IPR_PALtemp20
:
391 case AlphaISA::IPR_PALtemp21
:
392 case AlphaISA::IPR_PALtemp22
:
393 case AlphaISA::IPR_PAL_BASE
:
394 case AlphaISA::IPR_IC_PERR_STAT
:
395 case AlphaISA::IPR_DC_PERR_STAT
:
396 case AlphaISA::IPR_PMCTR
:
397 // write entire quad w/ no side-effect
401 case AlphaISA::IPR_CC_CTL
:
402 // This IPR resets the cycle counter. We assume this only
403 // happens once... let's verify that.
404 assert(ipr
[idx
] == 0);
408 case AlphaISA::IPR_CC
:
409 // This IPR only writes the upper 64 bits. It's ok to write
410 // all 64 here since we mask out the lower 32 in rpcc (see
415 case AlphaISA::IPR_PALtemp23
:
416 // write entire quad w/ no side-effect
419 kernelStats
->context(old
, val
);
422 case AlphaISA::IPR_DTB_PTE
:
423 // write entire quad w/ no side-effect, tag is forthcoming
427 case AlphaISA::IPR_EXC_ADDR
:
428 // second least significant bit in PC is always zero
432 case AlphaISA::IPR_ASTRR
:
433 case AlphaISA::IPR_ASTER
:
434 // only write least significant four bits - privilege mask
435 ipr
[idx
] = val
& 0xf;
438 case AlphaISA::IPR_IPLR
:
440 if (break_ipl
!= -1 && break_ipl
== (val
& 0x1f))
444 // only write least significant five bits - interrupt level
445 ipr
[idx
] = val
& 0x1f;
446 kernelStats
->swpipl(ipr
[idx
]);
449 case AlphaISA::IPR_DTB_CM
:
451 kernelStats
->mode(Kernel::user
);
453 kernelStats
->mode(Kernel::kernel
);
455 case AlphaISA::IPR_ICM
:
456 // only write two mode bits - processor mode
457 ipr
[idx
] = val
& 0x18;
460 case AlphaISA::IPR_ALT_MODE
:
461 // only write two mode bits - processor mode
462 ipr
[idx
] = val
& 0x18;
465 case AlphaISA::IPR_MCSR
:
466 // more here after optimization...
470 case AlphaISA::IPR_SIRR
:
471 // only write software interrupt mask
472 ipr
[idx
] = val
& 0x7fff0;
475 case AlphaISA::IPR_ICSR
:
476 ipr
[idx
] = val
& ULL(0xffffff0300);
479 case AlphaISA::IPR_IVPTBR
:
480 case AlphaISA::IPR_MVPTBR
:
481 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
484 case AlphaISA::IPR_DC_TEST_CTL
:
485 ipr
[idx
] = val
& 0x1ffb;
488 case AlphaISA::IPR_DC_MODE
:
489 case AlphaISA::IPR_MAF_MODE
:
490 ipr
[idx
] = val
& 0x3f;
493 case AlphaISA::IPR_ITB_ASN
:
494 ipr
[idx
] = val
& 0x7f0;
497 case AlphaISA::IPR_DTB_ASN
:
498 ipr
[idx
] = val
& ULL(0xfe00000000000000);
501 case AlphaISA::IPR_EXC_SUM
:
502 case AlphaISA::IPR_EXC_MASK
:
503 // any write to this register clears it
507 case AlphaISA::IPR_INTID
:
508 case AlphaISA::IPR_SL_RCV
:
509 case AlphaISA::IPR_MM_STAT
:
510 case AlphaISA::IPR_ITB_PTE_TEMP
:
511 case AlphaISA::IPR_DTB_PTE_TEMP
:
512 // read-only registers
513 return Unimplemented_Opcode_Fault
;
515 case AlphaISA::IPR_HWINT_CLR
:
516 case AlphaISA::IPR_SL_XMIT
:
517 case AlphaISA::IPR_DC_FLUSH
:
518 case AlphaISA::IPR_IC_FLUSH
:
519 // the following are write only
523 case AlphaISA::IPR_DTB_IA
:
524 // really a control write
530 case AlphaISA::IPR_DTB_IAP
:
531 // really a control write
534 dtb
->flushProcesses();
537 case AlphaISA::IPR_DTB_IS
:
538 // really a control write
541 dtb
->flushAddr(val
, DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
544 case AlphaISA::IPR_DTB_TAG
: {
545 struct AlphaISA::PTE pte
;
547 // FIXME: granularity hints NYI...
548 if (DTB_PTE_GH(ipr
[AlphaISA::IPR_DTB_PTE
]) != 0)
549 panic("PTE GH field != 0");
554 // construct PTE for new entry
555 pte
.ppn
= DTB_PTE_PPN(ipr
[AlphaISA::IPR_DTB_PTE
]);
556 pte
.xre
= DTB_PTE_XRE(ipr
[AlphaISA::IPR_DTB_PTE
]);
557 pte
.xwe
= DTB_PTE_XWE(ipr
[AlphaISA::IPR_DTB_PTE
]);
558 pte
.fonr
= DTB_PTE_FONR(ipr
[AlphaISA::IPR_DTB_PTE
]);
559 pte
.fonw
= DTB_PTE_FONW(ipr
[AlphaISA::IPR_DTB_PTE
]);
560 pte
.asma
= DTB_PTE_ASMA(ipr
[AlphaISA::IPR_DTB_PTE
]);
561 pte
.asn
= DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]);
563 // insert new TAG/PTE value into data TLB
564 dtb
->insert(val
, pte
);
568 case AlphaISA::IPR_ITB_PTE
: {
569 struct AlphaISA::PTE pte
;
571 // FIXME: granularity hints NYI...
572 if (ITB_PTE_GH(val
) != 0)
573 panic("PTE GH field != 0");
578 // construct PTE for new entry
579 pte
.ppn
= ITB_PTE_PPN(val
);
580 pte
.xre
= ITB_PTE_XRE(val
);
582 pte
.fonr
= ITB_PTE_FONR(val
);
583 pte
.fonw
= ITB_PTE_FONW(val
);
584 pte
.asma
= ITB_PTE_ASMA(val
);
585 pte
.asn
= ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]);
587 // insert new TAG/PTE value into data TLB
588 itb
->insert(ipr
[AlphaISA::IPR_ITB_TAG
], pte
);
592 case AlphaISA::IPR_ITB_IA
:
593 // really a control write
599 case AlphaISA::IPR_ITB_IAP
:
600 // really a control write
603 itb
->flushProcesses();
606 case AlphaISA::IPR_ITB_IS
:
607 // really a control write
610 itb
->flushAddr(val
, ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]));
615 return Unimplemented_Opcode_Fault
;
623 * Check for special simulator handling of specific PAL calls.
624 * If return value is false, actual PAL call will be suppressed.
627 ExecContext::simPalCheck(int palFunc
)
629 kernelStats
->callpal(palFunc
);
634 if (--System::numSystemsRunning
== 0)
635 new SimExitEvent("all cpus halted");
640 if (system
->breakpoint())
648 //Forward instantiation for FastCPU object
650 void AlphaISA::processInterrupts(FastCPU
*xc
);
652 //Forward instantiation for FastCPU object
654 void AlphaISA::zeroRegisters(FastCPU
*xc
);
656 #endif // FULL_SYSTEM