3 #include "arch/alpha/alpha_memory.hh"
4 #include "arch/alpha/isa_traits.hh"
5 #include "arch/alpha/osfpal.hh"
7 #include "base/remote_gdb.hh"
8 #include "base/stats/events.hh"
9 #include "cpu/exec_context.hh"
10 #include "sim/debug.hh"
11 #include "sim/sim_events.hh"
16 #error This code is only valid for EV5 systems
19 ////////////////////////////////////////////////////////////////////////
24 AlphaISA::swap_palshadow(RegFile
*regs
, bool use_shadow
)
26 if (regs
->pal_shadow
== use_shadow
)
27 panic("swap_palshadow: wrong PAL shadow state");
29 regs
->pal_shadow
= use_shadow
;
31 for (int i
= 0; i
< NumIntRegs
; i
++) {
33 IntReg temp
= regs
->intRegFile
[i
];
34 regs
->intRegFile
[i
] = regs
->palregs
[i
];
35 regs
->palregs
[i
] = temp
;
40 ////////////////////////////////////////////////////////////////////////
42 // Machine dependent functions
45 AlphaISA::initCPU(RegFile
*regs
)
48 // CPU comes up with PAL regs enabled
49 swap_palshadow(regs
, true);
51 regs
->pc
= regs
->ipr
[IPR_PAL_BASE
] + fault_addr
[Reset_Fault
];
52 regs
->npc
= regs
->pc
+ sizeof(MachInst
);
55 ////////////////////////////////////////////////////////////////////////
57 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
60 AlphaISA::fault_addr
[Num_Faults
] = {
61 0x0000, /* No_Fault */
62 0x0001, /* Reset_Fault */
63 0x0401, /* Machine_Check_Fault */
64 0x0501, /* Arithmetic_Fault */
65 0x0101, /* Interrupt_Fault */
66 0x0201, /* Ndtb_Miss_Fault */
67 0x0281, /* Pdtb_Miss_Fault */
68 0x0301, /* Alignment_Fault */
69 0x0381, /* DTB_Fault_Fault */
70 0x0381, /* DTB_Acv_Fault */
71 0x0181, /* ITB_Miss_Fault */
72 0x0181, /* ITB_Fault_Fault */
73 0x0081, /* ITB_Acv_Fault */
74 0x0481, /* Unimplemented_Opcode_Fault */
75 0x0581, /* Fen_Fault */
76 0x2001, /* Pal_Fault */
77 0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
80 const int AlphaISA::reg_redir
[AlphaISA::NumIntRegs
] = {
81 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
82 /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
83 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
84 /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
86 ////////////////////////////////////////////////////////////////////////
91 AlphaISA::initIPRs(RegFile
*regs
)
93 uint64_t *ipr
= regs
->ipr
;
95 bzero((char *)ipr
, NumInternalProcRegs
* sizeof(InternalProcReg
));
96 ipr
[IPR_PAL_BASE
] = PAL_BASE
;
102 ExecContext::ev5_trap(Fault fault
)
104 Stats::recordEvent(csprintf("Fault %s", FaultName(fault
)));
106 assert(!misspeculating());
107 kernelStats
.fault(fault
);
109 if (fault
== Arithmetic_Fault
)
110 panic("Arithmetic traps are unimplemented!");
112 AlphaISA::InternalProcReg
*ipr
= regs
.ipr
;
114 // exception restart address
115 if (fault
!= Interrupt_Fault
|| !PC_PAL(regs
.pc
))
116 ipr
[AlphaISA::IPR_EXC_ADDR
] = regs
.pc
;
118 if (fault
== Pal_Fault
|| fault
== Arithmetic_Fault
/* ||
119 fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
120 // traps... skip faulting instruction
121 ipr
[AlphaISA::IPR_EXC_ADDR
] += 4;
124 if (!PC_PAL(regs
.pc
))
125 AlphaISA::swap_palshadow(®s
, true);
127 regs
.pc
= ipr
[AlphaISA::IPR_PAL_BASE
] + AlphaISA::fault_addr
[fault
];
128 regs
.npc
= regs
.pc
+ sizeof(MachInst
);
133 AlphaISA::intr_post(RegFile
*regs
, Fault fault
, Addr pc
)
135 InternalProcReg
*ipr
= regs
->ipr
;
136 bool use_pc
= (fault
== No_Fault
);
138 if (fault
== Arithmetic_Fault
)
139 panic("arithmetic faults NYI...");
141 // compute exception restart address
142 if (use_pc
|| fault
== Pal_Fault
|| fault
== Arithmetic_Fault
) {
143 // traps... skip faulting instruction
144 ipr
[IPR_EXC_ADDR
] = regs
->pc
+ 4;
146 // fault, post fault at excepting instruction
147 ipr
[IPR_EXC_ADDR
] = regs
->pc
;
150 // jump to expection address (PAL PC bit set here as well...)
152 regs
->npc
= ipr
[IPR_PAL_BASE
] + fault_addr
[fault
];
154 regs
->npc
= ipr
[IPR_PAL_BASE
] + pc
;
156 // that's it! (orders of magnitude less painful than x86)
159 bool AlphaISA::check_interrupts
= false;
164 uint64_t *ipr
= regs
.ipr
;
166 if (!PC_PAL(regs
.pc
))
167 return Unimplemented_Opcode_Fault
;
169 setNextPC(ipr
[AlphaISA::IPR_EXC_ADDR
]);
171 if (!misspeculating()) {
174 if ((ipr
[AlphaISA::IPR_EXC_ADDR
] & 1) == 0)
175 AlphaISA::swap_palshadow(®s
, false);
177 AlphaISA::check_interrupts
= true;
180 // FIXME: XXX check for interrupts? XXX
185 ExecContext::readIpr(int idx
, Fault
&fault
)
187 uint64_t *ipr
= regs
.ipr
;
188 uint64_t retval
= 0; // return value, default 0
191 case AlphaISA::IPR_PALtemp0
:
192 case AlphaISA::IPR_PALtemp1
:
193 case AlphaISA::IPR_PALtemp2
:
194 case AlphaISA::IPR_PALtemp3
:
195 case AlphaISA::IPR_PALtemp4
:
196 case AlphaISA::IPR_PALtemp5
:
197 case AlphaISA::IPR_PALtemp6
:
198 case AlphaISA::IPR_PALtemp7
:
199 case AlphaISA::IPR_PALtemp8
:
200 case AlphaISA::IPR_PALtemp9
:
201 case AlphaISA::IPR_PALtemp10
:
202 case AlphaISA::IPR_PALtemp11
:
203 case AlphaISA::IPR_PALtemp12
:
204 case AlphaISA::IPR_PALtemp13
:
205 case AlphaISA::IPR_PALtemp14
:
206 case AlphaISA::IPR_PALtemp15
:
207 case AlphaISA::IPR_PALtemp16
:
208 case AlphaISA::IPR_PALtemp17
:
209 case AlphaISA::IPR_PALtemp18
:
210 case AlphaISA::IPR_PALtemp19
:
211 case AlphaISA::IPR_PALtemp20
:
212 case AlphaISA::IPR_PALtemp21
:
213 case AlphaISA::IPR_PALtemp22
:
214 case AlphaISA::IPR_PALtemp23
:
215 case AlphaISA::IPR_PAL_BASE
:
217 case AlphaISA::IPR_IVPTBR
:
218 case AlphaISA::IPR_DC_MODE
:
219 case AlphaISA::IPR_MAF_MODE
:
220 case AlphaISA::IPR_ISR
:
221 case AlphaISA::IPR_EXC_ADDR
:
222 case AlphaISA::IPR_IC_PERR_STAT
:
223 case AlphaISA::IPR_DC_PERR_STAT
:
224 case AlphaISA::IPR_MCSR
:
225 case AlphaISA::IPR_ASTRR
:
226 case AlphaISA::IPR_ASTER
:
227 case AlphaISA::IPR_SIRR
:
228 case AlphaISA::IPR_ICSR
:
229 case AlphaISA::IPR_ICM
:
230 case AlphaISA::IPR_DTB_CM
:
231 case AlphaISA::IPR_IPLR
:
232 case AlphaISA::IPR_INTID
:
233 case AlphaISA::IPR_PMCTR
:
238 case AlphaISA::IPR_CC
:
239 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
240 retval
|= curTick
& ULL(0x00000000ffffffff);
243 case AlphaISA::IPR_VA
:
244 // SFX: unlocks interrupt status registers
247 if (!misspeculating())
248 regs
.intrlock
= false;
251 case AlphaISA::IPR_VA_FORM
:
252 case AlphaISA::IPR_MM_STAT
:
253 case AlphaISA::IPR_IFAULT_VA_FORM
:
254 case AlphaISA::IPR_EXC_MASK
:
255 case AlphaISA::IPR_EXC_SUM
:
259 case AlphaISA::IPR_DTB_PTE
:
261 AlphaISA::PTE
&pte
= dtb
->index(!misspeculating());
263 retval
|= ((u_int64_t
)pte
.ppn
& ULL(0x7ffffff)) << 32;
264 retval
|= ((u_int64_t
)pte
.xre
& ULL(0xf)) << 8;
265 retval
|= ((u_int64_t
)pte
.xwe
& ULL(0xf)) << 12;
266 retval
|= ((u_int64_t
)pte
.fonr
& ULL(0x1)) << 1;
267 retval
|= ((u_int64_t
)pte
.fonw
& ULL(0x1))<< 2;
268 retval
|= ((u_int64_t
)pte
.asma
& ULL(0x1)) << 4;
269 retval
|= ((u_int64_t
)pte
.asn
& ULL(0x7f)) << 57;
273 // write only registers
274 case AlphaISA::IPR_HWINT_CLR
:
275 case AlphaISA::IPR_SL_XMIT
:
276 case AlphaISA::IPR_DC_FLUSH
:
277 case AlphaISA::IPR_IC_FLUSH
:
278 case AlphaISA::IPR_ALT_MODE
:
279 case AlphaISA::IPR_DTB_IA
:
280 case AlphaISA::IPR_DTB_IAP
:
281 case AlphaISA::IPR_ITB_IA
:
282 case AlphaISA::IPR_ITB_IAP
:
283 fault
= Unimplemented_Opcode_Fault
;
288 fault
= Unimplemented_Opcode_Fault
;
296 // Cause the simulator to break when changing to the following IPL
301 ExecContext::setIpr(int idx
, uint64_t val
)
303 uint64_t *ipr
= regs
.ipr
;
306 if (misspeculating())
310 case AlphaISA::IPR_PALtemp0
:
311 case AlphaISA::IPR_PALtemp1
:
312 case AlphaISA::IPR_PALtemp2
:
313 case AlphaISA::IPR_PALtemp3
:
314 case AlphaISA::IPR_PALtemp4
:
315 case AlphaISA::IPR_PALtemp5
:
316 case AlphaISA::IPR_PALtemp6
:
317 case AlphaISA::IPR_PALtemp7
:
318 case AlphaISA::IPR_PALtemp8
:
319 case AlphaISA::IPR_PALtemp9
:
320 case AlphaISA::IPR_PALtemp10
:
321 case AlphaISA::IPR_PALtemp11
:
322 case AlphaISA::IPR_PALtemp12
:
323 case AlphaISA::IPR_PALtemp13
:
324 case AlphaISA::IPR_PALtemp14
:
325 case AlphaISA::IPR_PALtemp15
:
326 case AlphaISA::IPR_PALtemp16
:
327 case AlphaISA::IPR_PALtemp17
:
328 case AlphaISA::IPR_PALtemp18
:
329 case AlphaISA::IPR_PALtemp19
:
330 case AlphaISA::IPR_PALtemp20
:
331 case AlphaISA::IPR_PALtemp21
:
332 case AlphaISA::IPR_PALtemp22
:
333 case AlphaISA::IPR_PAL_BASE
:
334 case AlphaISA::IPR_IC_PERR_STAT
:
335 case AlphaISA::IPR_DC_PERR_STAT
:
336 case AlphaISA::IPR_PMCTR
:
337 // write entire quad w/ no side-effect
341 case AlphaISA::IPR_CC_CTL
:
342 // This IPR resets the cycle counter. We assume this only
343 // happens once... let's verify that.
344 assert(ipr
[idx
] == 0);
348 case AlphaISA::IPR_CC
:
349 // This IPR only writes the upper 64 bits. It's ok to write
350 // all 64 here since we mask out the lower 32 in rpcc (see
355 case AlphaISA::IPR_PALtemp23
:
356 // write entire quad w/ no side-effect
359 kernelStats
.context(old
, val
);
362 case AlphaISA::IPR_DTB_PTE
:
363 // write entire quad w/ no side-effect, tag is forthcoming
367 case AlphaISA::IPR_EXC_ADDR
:
368 // second least significant bit in PC is always zero
372 case AlphaISA::IPR_ASTRR
:
373 case AlphaISA::IPR_ASTER
:
374 // only write least significant four bits - privilege mask
375 ipr
[idx
] = val
& 0xf;
378 case AlphaISA::IPR_IPLR
:
380 if (break_ipl
!= -1 && break_ipl
== (val
& 0x1f))
384 // only write least significant five bits - interrupt level
385 ipr
[idx
] = val
& 0x1f;
386 kernelStats
.swpipl(ipr
[idx
]);
389 case AlphaISA::IPR_DTB_CM
:
390 kernelStats
.mode((val
& 0x18) != 0);
392 case AlphaISA::IPR_ICM
:
393 // only write two mode bits - processor mode
394 ipr
[idx
] = val
& 0x18;
397 case AlphaISA::IPR_ALT_MODE
:
398 // only write two mode bits - processor mode
399 ipr
[idx
] = val
& 0x18;
402 case AlphaISA::IPR_MCSR
:
403 // more here after optimization...
407 case AlphaISA::IPR_SIRR
:
408 // only write software interrupt mask
409 ipr
[idx
] = val
& 0x7fff0;
412 case AlphaISA::IPR_ICSR
:
413 ipr
[idx
] = val
& ULL(0xffffff0300);
416 case AlphaISA::IPR_IVPTBR
:
417 case AlphaISA::IPR_MVPTBR
:
418 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
421 case AlphaISA::IPR_DC_TEST_CTL
:
422 ipr
[idx
] = val
& 0x1ffb;
425 case AlphaISA::IPR_DC_MODE
:
426 case AlphaISA::IPR_MAF_MODE
:
427 ipr
[idx
] = val
& 0x3f;
430 case AlphaISA::IPR_ITB_ASN
:
431 ipr
[idx
] = val
& 0x7f0;
434 case AlphaISA::IPR_DTB_ASN
:
435 ipr
[idx
] = val
& ULL(0xfe00000000000000);
438 case AlphaISA::IPR_EXC_SUM
:
439 case AlphaISA::IPR_EXC_MASK
:
440 // any write to this register clears it
444 case AlphaISA::IPR_INTID
:
445 case AlphaISA::IPR_SL_RCV
:
446 case AlphaISA::IPR_MM_STAT
:
447 case AlphaISA::IPR_ITB_PTE_TEMP
:
448 case AlphaISA::IPR_DTB_PTE_TEMP
:
449 // read-only registers
450 return Unimplemented_Opcode_Fault
;
452 case AlphaISA::IPR_HWINT_CLR
:
453 case AlphaISA::IPR_SL_XMIT
:
454 case AlphaISA::IPR_DC_FLUSH
:
455 case AlphaISA::IPR_IC_FLUSH
:
456 // the following are write only
460 case AlphaISA::IPR_DTB_IA
:
461 // really a control write
467 case AlphaISA::IPR_DTB_IAP
:
468 // really a control write
471 dtb
->flushProcesses();
474 case AlphaISA::IPR_DTB_IS
:
475 // really a control write
478 dtb
->flushAddr(val
, DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
481 case AlphaISA::IPR_DTB_TAG
: {
482 struct AlphaISA::PTE pte
;
484 // FIXME: granularity hints NYI...
485 if (DTB_PTE_GH(ipr
[AlphaISA::IPR_DTB_PTE
]) != 0)
486 panic("PTE GH field != 0");
491 // construct PTE for new entry
492 pte
.ppn
= DTB_PTE_PPN(ipr
[AlphaISA::IPR_DTB_PTE
]);
493 pte
.xre
= DTB_PTE_XRE(ipr
[AlphaISA::IPR_DTB_PTE
]);
494 pte
.xwe
= DTB_PTE_XWE(ipr
[AlphaISA::IPR_DTB_PTE
]);
495 pte
.fonr
= DTB_PTE_FONR(ipr
[AlphaISA::IPR_DTB_PTE
]);
496 pte
.fonw
= DTB_PTE_FONW(ipr
[AlphaISA::IPR_DTB_PTE
]);
497 pte
.asma
= DTB_PTE_ASMA(ipr
[AlphaISA::IPR_DTB_PTE
]);
498 pte
.asn
= DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]);
500 // insert new TAG/PTE value into data TLB
501 dtb
->insert(val
, pte
);
505 case AlphaISA::IPR_ITB_PTE
: {
506 struct AlphaISA::PTE pte
;
508 // FIXME: granularity hints NYI...
509 if (ITB_PTE_GH(val
) != 0)
510 panic("PTE GH field != 0");
515 // construct PTE for new entry
516 pte
.ppn
= ITB_PTE_PPN(val
);
517 pte
.xre
= ITB_PTE_XRE(val
);
519 pte
.fonr
= ITB_PTE_FONR(val
);
520 pte
.fonw
= ITB_PTE_FONW(val
);
521 pte
.asma
= ITB_PTE_ASMA(val
);
522 pte
.asn
= ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]);
524 // insert new TAG/PTE value into data TLB
525 itb
->insert(ipr
[AlphaISA::IPR_ITB_TAG
], pte
);
529 case AlphaISA::IPR_ITB_IA
:
530 // really a control write
536 case AlphaISA::IPR_ITB_IAP
:
537 // really a control write
540 itb
->flushProcesses();
543 case AlphaISA::IPR_ITB_IS
:
544 // really a control write
547 itb
->flushAddr(val
, ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]));
552 return Unimplemented_Opcode_Fault
;
560 * Check for special simulator handling of specific PAL calls.
561 * If return value is false, actual PAL call will be suppressed.
564 ExecContext::simPalCheck(int palFunc
)
566 kernelStats
.callpal(palFunc
);
571 if (--System::numSystemsRunning
== 0)
572 new SimExitEvent("all cpus halted");
577 if (system
->breakpoint())
585 #endif // FULL_SYSTEM