arch/alpha/ev5.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/alpha/alpha_memory.hh"
  30 #include "arch/alpha/isa_traits.hh"
  31 #include "arch/alpha/osfpal.hh"
  32 #include "base/kgdb.h"
  33 #include "base/remote_gdb.hh"
  34 #include "base/stats/events.hh"
  35 #include "config/full_system.hh"
  36 #include "cpu/base.hh"
  37 #include "cpu/exec_context.hh"
  38 #include "cpu/fast/cpu.hh"
  39 #include "kern/kernel_stats.hh"
  40 #include "sim/debug.hh"
  41 #include "sim/sim_events.hh"
  42
  43 #if FULL_SYSTEM
  44
  45 using namespace EV5;
  46
  47 ////////////////////////////////////////////////////////////////////////
  48 //
  49 //
  50 //
  51 void
  52 AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
  53 {
  54     if (regs->pal_shadow == use_shadow)
  55         panic("swap_palshadow: wrong PAL shadow state");
  56
  57     regs->pal_shadow = use_shadow;
  58
  59     for (int i = 0; i < NumIntRegs; i++) {
  60         if (reg_redir[i]) {
  61             IntReg temp = regs->intRegFile[i];
  62             regs->intRegFile[i] = regs->palregs[i];
  63             regs->palregs[i] = temp;
  64         }
  65     }
  66 }
  67
  68 ////////////////////////////////////////////////////////////////////////
  69 //
  70 //  Machine dependent functions
  71 //
  72 void
  73 AlphaISA::initCPU(RegFile *regs)
  74 {
  75     initIPRs(regs);
  76     // CPU comes up with PAL regs enabled
  77     swap_palshadow(regs, true);
  78
  79     regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
  80     regs->npc = regs->pc + sizeof(MachInst);
  81 }
  82
  83 ////////////////////////////////////////////////////////////////////////
  84 //
  85 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
  86 //
  87 const Addr
  88 AlphaISA::fault_addr(Fault * fault)
  89 {
  90         //Check for the system wide faults
  91         if(fault == NoFault) return 0x0000;
  92         else if(fault == MachineCheckFault) return 0x0401;
  93         else if(fault == AlignmentFault) return 0x0301;
  94         else if(fault == FakeMemFault) return 0x0000;
  95         //Deal with the alpha specific faults
  96         return ((AlphaFault*)fault)->vect;
  97 };
  98
  99 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
 100     /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
 101     /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
 102     /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
 103     /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
 104
 105 ////////////////////////////////////////////////////////////////////////
 106 //
 107 //
 108 //
 109 void
 110 AlphaISA::initIPRs(RegFile *regs)
 111 {
 112     uint64_t *ipr = regs->ipr;
 113
 114     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
 115     ipr[IPR_PAL_BASE] = PalBase;
 116     ipr[IPR_MCSR] = 0x6;
 117 }
 118
 119
 120 template <class CPU>
 121 void
 122 AlphaISA::processInterrupts(CPU *cpu)
 123 {
 124     //Check if there are any outstanding interrupts
 125     //Handle the interrupts
 126     int ipl = 0;
 127     int summary = 0;
 128     IntReg *ipr = cpu->getIprPtr();
 129
 130     cpu->checkInterrupts = false;
 131
 132     if (ipr[IPR_ASTRR])
 133         panic("asynchronous traps not implemented\n");
 134
 135     if (ipr[IPR_SIRR]) {
 136         for (int i = INTLEVEL_SOFTWARE_MIN;
 137              i < INTLEVEL_SOFTWARE_MAX; i++) {
 138             if (ipr[IPR_SIRR] & (ULL(1) << i)) {
 139                 // See table 4-19 of the 21164 hardware reference
 140                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
 141                 summary |= (ULL(1) << i);
 142             }
 143         }
 144     }
 145
 146     uint64_t interrupts = cpu->intr_status();
 147
 148     if (interrupts) {
 149         for (int i = INTLEVEL_EXTERNAL_MIN;
 150              i < INTLEVEL_EXTERNAL_MAX; i++) {
 151             if (interrupts & (ULL(1) << i)) {
 152                 // See table 4-19 of the 21164 hardware reference
 153                 ipl = i;
 154                 summary |= (ULL(1) << i);
 155             }
 156         }
 157     }
 158
 159     if (ipl && ipl > ipr[IPR_IPLR]) {
 160         ipr[IPR_ISR] = summary;
 161         ipr[IPR_INTID] = ipl;
 162         cpu->trap(InterruptFault);
 163         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 164                 ipr[IPR_IPLR], ipl, summary);
 165     }
 166
 167 }
 168
 169 template <class CPU>
 170 void
 171 AlphaISA::zeroRegisters(CPU *cpu)
 172 {
 173     // Insure ISA semantics
 174     // (no longer very clean due to the change in setIntReg() in the
 175     // cpu model.  Consider changing later.)
 176     cpu->xc->setIntReg(ZeroReg, 0);
 177     cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
 178 }
 179
 180 void
 181 ExecContext::ev5_trap(Fault * fault)
 182 {
 183     DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
 184     cpu->recordEvent(csprintf("Fault %s", fault->name));
 185
 186     assert(!misspeculating());
 187     kernelStats->fault(fault);
 188
 189     if (fault == ArithmeticFault)
 190         panic("Arithmetic traps are unimplemented!");
 191
 192     AlphaISA::InternalProcReg *ipr = regs.ipr;
 193
 194     // exception restart address
 195     if (fault != InterruptFault || !inPalMode())
 196         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 197
 198     if (fault == PalFault || fault == ArithmeticFault /* ||
 199         fault == InterruptFault && !inPalMode() */) {
 200         // traps...  skip faulting instruction
 201         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
 202     }
 203
 204     if (!inPalMode())
 205         AlphaISA::swap_palshadow(&regs, true);
 206
 207     regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
 208     regs.npc = regs.pc + sizeof(MachInst);
 209 }
 210
 211
 212 void
 213 AlphaISA::intr_post(RegFile *regs, Fault * fault, Addr pc)
 214 {
 215     InternalProcReg *ipr = regs->ipr;
 216     bool use_pc = (fault == NoFault);
 217
 218     if (fault == ArithmeticFault)
 219         panic("arithmetic faults NYI...");
 220
 221     // compute exception restart address
 222     if (use_pc || fault == PalFault || fault == ArithmeticFault) {
 223         // traps...  skip faulting instruction
 224         ipr[IPR_EXC_ADDR] = regs->pc + 4;
 225     } else {
 226         // fault, post fault at excepting instruction
 227         ipr[IPR_EXC_ADDR] = regs->pc;
 228     }
 229
 230     // jump to expection address (PAL PC bit set here as well...)
 231     if (!use_pc)
 232         regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
 233     else
 234         regs->npc = ipr[IPR_PAL_BASE] + pc;
 235
 236     // that's it! (orders of magnitude less painful than x86)
 237 }
 238
 239 Fault *
 240 ExecContext::hwrei()
 241 {
 242     uint64_t *ipr = regs.ipr;
 243
 244     if (!inPalMode())
 245         return UnimplementedOpcodeFault;
 246
 247     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 248
 249     if (!misspeculating()) {
 250         kernelStats->hwrei();
 251
 252         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
 253             AlphaISA::swap_palshadow(&regs, false);
 254
 255         cpu->checkInterrupts = true;
 256     }
 257
 258     // FIXME: XXX check for interrupts? XXX
 259     return NoFault;
 260 }
 261
 262 uint64_t
 263 ExecContext::readIpr(int idx, Fault * &fault)
 264 {
 265     uint64_t *ipr = regs.ipr;
 266     uint64_t retval = 0;        // return value, default 0
 267
 268     switch (idx) {
 269       case AlphaISA::IPR_PALtemp0:
 270       case AlphaISA::IPR_PALtemp1:
 271       case AlphaISA::IPR_PALtemp2:
 272       case AlphaISA::IPR_PALtemp3:
 273       case AlphaISA::IPR_PALtemp4:
 274       case AlphaISA::IPR_PALtemp5:
 275       case AlphaISA::IPR_PALtemp6:
 276       case AlphaISA::IPR_PALtemp7:
 277       case AlphaISA::IPR_PALtemp8:
 278       case AlphaISA::IPR_PALtemp9:
 279       case AlphaISA::IPR_PALtemp10:
 280       case AlphaISA::IPR_PALtemp11:
 281       case AlphaISA::IPR_PALtemp12:
 282       case AlphaISA::IPR_PALtemp13:
 283       case AlphaISA::IPR_PALtemp14:
 284       case AlphaISA::IPR_PALtemp15:
 285       case AlphaISA::IPR_PALtemp16:
 286       case AlphaISA::IPR_PALtemp17:
 287       case AlphaISA::IPR_PALtemp18:
 288       case AlphaISA::IPR_PALtemp19:
 289       case AlphaISA::IPR_PALtemp20:
 290       case AlphaISA::IPR_PALtemp21:
 291       case AlphaISA::IPR_PALtemp22:
 292       case AlphaISA::IPR_PALtemp23:
 293       case AlphaISA::IPR_PAL_BASE:
 294
 295       case AlphaISA::IPR_IVPTBR:
 296       case AlphaISA::IPR_DC_MODE:
 297       case AlphaISA::IPR_MAF_MODE:
 298       case AlphaISA::IPR_ISR:
 299       case AlphaISA::IPR_EXC_ADDR:
 300       case AlphaISA::IPR_IC_PERR_STAT:
 301       case AlphaISA::IPR_DC_PERR_STAT:
 302       case AlphaISA::IPR_MCSR:
 303       case AlphaISA::IPR_ASTRR:
 304       case AlphaISA::IPR_ASTER:
 305       case AlphaISA::IPR_SIRR:
 306       case AlphaISA::IPR_ICSR:
 307       case AlphaISA::IPR_ICM:
 308       case AlphaISA::IPR_DTB_CM:
 309       case AlphaISA::IPR_IPLR:
 310       case AlphaISA::IPR_INTID:
 311       case AlphaISA::IPR_PMCTR:
 312         // no side-effect
 313         retval = ipr[idx];
 314         break;
 315
 316       case AlphaISA::IPR_CC:
 317         retval |= ipr[idx] & ULL(0xffffffff00000000);
 318         retval |= cpu->curCycle()  & ULL(0x00000000ffffffff);
 319         break;
 320
 321       case AlphaISA::IPR_VA:
 322         retval = ipr[idx];
 323         break;
 324
 325       case AlphaISA::IPR_VA_FORM:
 326       case AlphaISA::IPR_MM_STAT:
 327       case AlphaISA::IPR_IFAULT_VA_FORM:
 328       case AlphaISA::IPR_EXC_MASK:
 329       case AlphaISA::IPR_EXC_SUM:
 330         retval = ipr[idx];
 331         break;
 332
 333       case AlphaISA::IPR_DTB_PTE:
 334         {
 335             AlphaISA::PTE &pte = dtb->index(!misspeculating());
 336
 337             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
 338             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
 339             retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
 340             retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
 341             retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
 342             retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
 343             retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
 344         }
 345         break;
 346
 347         // write only registers
 348       case AlphaISA::IPR_HWINT_CLR:
 349       case AlphaISA::IPR_SL_XMIT:
 350       case AlphaISA::IPR_DC_FLUSH:
 351       case AlphaISA::IPR_IC_FLUSH:
 352       case AlphaISA::IPR_ALT_MODE:
 353       case AlphaISA::IPR_DTB_IA:
 354       case AlphaISA::IPR_DTB_IAP:
 355       case AlphaISA::IPR_ITB_IA:
 356       case AlphaISA::IPR_ITB_IAP:
 357         fault = UnimplementedOpcodeFault;
 358         break;
 359
 360       default:
 361         // invalid IPR
 362         fault = UnimplementedOpcodeFault;
 363         break;
 364     }
 365
 366     return retval;
 367 }
 368
 369 #ifdef DEBUG
 370 // Cause the simulator to break when changing to the following IPL
 371 int break_ipl = -1;
 372 #endif
 373
 374 Fault *
 375 ExecContext::setIpr(int idx, uint64_t val)
 376 {
 377     uint64_t *ipr = regs.ipr;
 378     uint64_t old;
 379
 380     if (misspeculating())
 381         return NoFault;
 382
 383     switch (idx) {
 384       case AlphaISA::IPR_PALtemp0:
 385       case AlphaISA::IPR_PALtemp1:
 386       case AlphaISA::IPR_PALtemp2:
 387       case AlphaISA::IPR_PALtemp3:
 388       case AlphaISA::IPR_PALtemp4:
 389       case AlphaISA::IPR_PALtemp5:
 390       case AlphaISA::IPR_PALtemp6:
 391       case AlphaISA::IPR_PALtemp7:
 392       case AlphaISA::IPR_PALtemp8:
 393       case AlphaISA::IPR_PALtemp9:
 394       case AlphaISA::IPR_PALtemp10:
 395       case AlphaISA::IPR_PALtemp11:
 396       case AlphaISA::IPR_PALtemp12:
 397       case AlphaISA::IPR_PALtemp13:
 398       case AlphaISA::IPR_PALtemp14:
 399       case AlphaISA::IPR_PALtemp15:
 400       case AlphaISA::IPR_PALtemp16:
 401       case AlphaISA::IPR_PALtemp17:
 402       case AlphaISA::IPR_PALtemp18:
 403       case AlphaISA::IPR_PALtemp19:
 404       case AlphaISA::IPR_PALtemp20:
 405       case AlphaISA::IPR_PALtemp21:
 406       case AlphaISA::IPR_PALtemp22:
 407       case AlphaISA::IPR_PAL_BASE:
 408       case AlphaISA::IPR_IC_PERR_STAT:
 409       case AlphaISA::IPR_DC_PERR_STAT:
 410       case AlphaISA::IPR_PMCTR:
 411         // write entire quad w/ no side-effect
 412         ipr[idx] = val;
 413         break;
 414
 415       case AlphaISA::IPR_CC_CTL:
 416         // This IPR resets the cycle counter.  We assume this only
 417         // happens once... let's verify that.
 418         assert(ipr[idx] == 0);
 419         ipr[idx] = 1;
 420         break;
 421
 422       case AlphaISA::IPR_CC:
 423         // This IPR only writes the upper 64 bits.  It's ok to write
 424         // all 64 here since we mask out the lower 32 in rpcc (see
 425         // isa_desc).
 426         ipr[idx] = val;
 427         break;
 428
 429       case AlphaISA::IPR_PALtemp23:
 430         // write entire quad w/ no side-effect
 431         old = ipr[idx];
 432         ipr[idx] = val;
 433         kernelStats->context(old, val);
 434         break;
 435
 436       case AlphaISA::IPR_DTB_PTE:
 437         // write entire quad w/ no side-effect, tag is forthcoming
 438         ipr[idx] = val;
 439         break;
 440
 441       case AlphaISA::IPR_EXC_ADDR:
 442         // second least significant bit in PC is always zero
 443         ipr[idx] = val & ~2;
 444         break;
 445
 446       case AlphaISA::IPR_ASTRR:
 447       case AlphaISA::IPR_ASTER:
 448         // only write least significant four bits - privilege mask
 449         ipr[idx] = val & 0xf;
 450         break;
 451
 452       case AlphaISA::IPR_IPLR:
 453 #ifdef DEBUG
 454         if (break_ipl != -1 && break_ipl == (val & 0x1f))
 455             debug_break();
 456 #endif
 457
 458         // only write least significant five bits - interrupt level
 459         ipr[idx] = val & 0x1f;
 460         kernelStats->swpipl(ipr[idx]);
 461         break;
 462
 463       case AlphaISA::IPR_DTB_CM:
 464         if (val & 0x18)
 465             kernelStats->mode(Kernel::user);
 466         else
 467             kernelStats->mode(Kernel::kernel);
 468
 469       case AlphaISA::IPR_ICM:
 470         // only write two mode bits - processor mode
 471         ipr[idx] = val & 0x18;
 472         break;
 473
 474       case AlphaISA::IPR_ALT_MODE:
 475         // only write two mode bits - processor mode
 476         ipr[idx] = val & 0x18;
 477         break;
 478
 479       case AlphaISA::IPR_MCSR:
 480         // more here after optimization...
 481         ipr[idx] = val;
 482         break;
 483
 484       case AlphaISA::IPR_SIRR:
 485         // only write software interrupt mask
 486         ipr[idx] = val & 0x7fff0;
 487         break;
 488
 489       case AlphaISA::IPR_ICSR:
 490         ipr[idx] = val & ULL(0xffffff0300);
 491         break;
 492
 493       case AlphaISA::IPR_IVPTBR:
 494       case AlphaISA::IPR_MVPTBR:
 495         ipr[idx] = val & ULL(0xffffffffc0000000);
 496         break;
 497
 498       case AlphaISA::IPR_DC_TEST_CTL:
 499         ipr[idx] = val & 0x1ffb;
 500         break;
 501
 502       case AlphaISA::IPR_DC_MODE:
 503       case AlphaISA::IPR_MAF_MODE:
 504         ipr[idx] = val & 0x3f;
 505         break;
 506
 507       case AlphaISA::IPR_ITB_ASN:
 508         ipr[idx] = val & 0x7f0;
 509         break;
 510
 511       case AlphaISA::IPR_DTB_ASN:
 512         ipr[idx] = val & ULL(0xfe00000000000000);
 513         break;
 514
 515       case AlphaISA::IPR_EXC_SUM:
 516       case AlphaISA::IPR_EXC_MASK:
 517         // any write to this register clears it
 518         ipr[idx] = 0;
 519         break;
 520
 521       case AlphaISA::IPR_INTID:
 522       case AlphaISA::IPR_SL_RCV:
 523       case AlphaISA::IPR_MM_STAT:
 524       case AlphaISA::IPR_ITB_PTE_TEMP:
 525       case AlphaISA::IPR_DTB_PTE_TEMP:
 526         // read-only registers
 527         return UnimplementedOpcodeFault;
 528
 529       case AlphaISA::IPR_HWINT_CLR:
 530       case AlphaISA::IPR_SL_XMIT:
 531       case AlphaISA::IPR_DC_FLUSH:
 532       case AlphaISA::IPR_IC_FLUSH:
 533         // the following are write only
 534         ipr[idx] = val;
 535         break;
 536
 537       case AlphaISA::IPR_DTB_IA:
 538         // really a control write
 539         ipr[idx] = 0;
 540
 541         dtb->flushAll();
 542         break;
 543
 544       case AlphaISA::IPR_DTB_IAP:
 545         // really a control write
 546         ipr[idx] = 0;
 547
 548         dtb->flushProcesses();
 549         break;
 550
 551       case AlphaISA::IPR_DTB_IS:
 552         // really a control write
 553         ipr[idx] = val;
 554
 555         dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
 556         break;
 557
 558       case AlphaISA::IPR_DTB_TAG: {
 559           struct AlphaISA::PTE pte;
 560
 561           // FIXME: granularity hints NYI...
 562           if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
 563               panic("PTE GH field != 0");
 564
 565           // write entire quad
 566           ipr[idx] = val;
 567
 568           // construct PTE for new entry
 569           pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
 570           pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
 571           pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
 572           pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
 573           pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
 574           pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
 575           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 576
 577           // insert new TAG/PTE value into data TLB
 578           dtb->insert(val, pte);
 579       }
 580         break;
 581
 582       case AlphaISA::IPR_ITB_PTE: {
 583           struct AlphaISA::PTE pte;
 584
 585           // FIXME: granularity hints NYI...
 586           if (ITB_PTE_GH(val) != 0)
 587               panic("PTE GH field != 0");
 588
 589           // write entire quad
 590           ipr[idx] = val;
 591
 592           // construct PTE for new entry
 593           pte.ppn = ITB_PTE_PPN(val);
 594           pte.xre = ITB_PTE_XRE(val);
 595           pte.xwe = 0;
 596           pte.fonr = ITB_PTE_FONR(val);
 597           pte.fonw = ITB_PTE_FONW(val);
 598           pte.asma = ITB_PTE_ASMA(val);
 599           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 600
 601           // insert new TAG/PTE value into data TLB
 602           itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
 603       }
 604         break;
 605
 606       case AlphaISA::IPR_ITB_IA:
 607         // really a control write
 608         ipr[idx] = 0;
 609
 610         itb->flushAll();
 611         break;
 612
 613       case AlphaISA::IPR_ITB_IAP:
 614         // really a control write
 615         ipr[idx] = 0;
 616
 617         itb->flushProcesses();
 618         break;
 619
 620       case AlphaISA::IPR_ITB_IS:
 621         // really a control write
 622         ipr[idx] = val;
 623
 624         itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
 625         break;
 626
 627       default:
 628         // invalid IPR
 629         return UnimplementedOpcodeFault;
 630     }
 631
 632     // no error...
 633     return NoFault;
 634 }
 635
 636 /**
 637  * Check for special simulator handling of specific PAL calls.
 638  * If return value is false, actual PAL call will be suppressed.
 639  */
 640 bool
 641 ExecContext::simPalCheck(int palFunc)
 642 {
 643     kernelStats->callpal(palFunc);
 644
 645     switch (palFunc) {
 646       case PAL::halt:
 647         halt();
 648         if (--System::numSystemsRunning == 0)
 649             new SimExitEvent("all cpus halted");
 650         break;
 651
 652       case PAL::bpt:
 653       case PAL::bugchk:
 654         if (system->breakpoint())
 655             return false;
 656         break;
 657     }
 658
 659     return true;
 660 }
 661
 662 //Forward instantiation for FastCPU object
 663 template
 664 void AlphaISA::processInterrupts(FastCPU *xc);
 665
 666 //Forward instantiation for FastCPU object
 667 template
 668 void AlphaISA::zeroRegisters(FastCPU *xc);
 669
 670 #endif // FULL_SYSTEM