arch/alpha/ev5.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/alpha/tlb.hh"
  30 #include "arch/alpha/isa_traits.hh"
  31 #include "arch/alpha/osfpal.hh"
  32 #include "base/kgdb.h"
  33 #include "base/remote_gdb.hh"
  34 #include "base/stats/events.hh"
  35 #include "config/full_system.hh"
  36 #include "cpu/base.hh"
  37 #include "cpu/exec_context.hh"
  38 #include "cpu/fast/cpu.hh"
  39 #include "kern/kernel_stats.hh"
  40 #include "sim/debug.hh"
  41 #include "sim/sim_events.hh"
  42
  43 #if FULL_SYSTEM
  44
  45 using namespace EV5;
  46
  47 ////////////////////////////////////////////////////////////////////////
  48 //
  49 //
  50 //
  51 void
  52 AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
  53 {
  54     if (regs->pal_shadow == use_shadow)
  55         panic("swap_palshadow: wrong PAL shadow state");
  56
  57     regs->pal_shadow = use_shadow;
  58
  59     for (int i = 0; i < NumIntRegs; i++) {
  60         if (reg_redir[i]) {
  61             IntReg temp = regs->intRegFile[i];
  62             regs->intRegFile[i] = regs->palregs[i];
  63             regs->palregs[i] = temp;
  64         }
  65     }
  66 }
  67
  68 ////////////////////////////////////////////////////////////////////////
  69 //
  70 //  Machine dependent functions
  71 //
  72 void
  73 AlphaISA::initCPU(RegFile *regs, int cpuId)
  74 {
  75     initIPRs(&regs->miscRegs, cpuId);
  76     // CPU comes up with PAL regs enabled
  77     swap_palshadow(regs, true);
  78
  79     regs->intRegFile[16] = cpuId;
  80     regs->intRegFile[0] = cpuId;
  81
  82     regs->pc = regs->miscRegs.readReg(IPR_PAL_BASE) + (new ResetFault)->vect();
  83     regs->npc = regs->pc + sizeof(MachInst);
  84 }
  85
  86 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
  87     /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
  88     /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
  89     /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
  90     /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
  91
  92 ////////////////////////////////////////////////////////////////////////
  93 //
  94 //
  95 //
  96 void
  97 AlphaISA::initIPRs(MiscRegFile *miscRegs, int cpuId)
  98 {
  99     miscRegs->clearIprs();
 100
 101     miscRegs->setReg(IPR_PAL_BASE, PalBase);
 102     miscRegs->setReg(IPR_MCSR, 0x6);
 103     miscRegs->setReg(IPR_PALtemp16, cpuId);
 104 }
 105
 106
 107 template <class CPU>
 108 void
 109 AlphaISA::processInterrupts(CPU *cpu)
 110 {
 111     //Check if there are any outstanding interrupts
 112     //Handle the interrupts
 113     int ipl = 0;
 114     int summary = 0;
 115
 116     cpu->checkInterrupts = false;
 117
 118     if (cpu->readMiscReg(IPR_ASTRR))
 119         panic("asynchronous traps not implemented\n");
 120
 121     if (cpu->readMiscReg(IPR_SIRR)) {
 122         for (int i = INTLEVEL_SOFTWARE_MIN;
 123              i < INTLEVEL_SOFTWARE_MAX; i++) {
 124             if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
 125                 // See table 4-19 of the 21164 hardware reference
 126                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
 127                 summary |= (ULL(1) << i);
 128             }
 129         }
 130     }
 131
 132     uint64_t interrupts = cpu->intr_status();
 133
 134     if (interrupts) {
 135         for (int i = INTLEVEL_EXTERNAL_MIN;
 136              i < INTLEVEL_EXTERNAL_MAX; i++) {
 137             if (interrupts & (ULL(1) << i)) {
 138                 // See table 4-19 of the 21164 hardware reference
 139                 ipl = i;
 140                 summary |= (ULL(1) << i);
 141             }
 142         }
 143     }
 144
 145     if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
 146         cpu->setMiscReg(IPR_ISR, summary);
 147         cpu->setMiscReg(IPR_INTID, ipl);
 148         cpu->trap(new InterruptFault);
 149         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 150                 cpu->readMiscReg(IPR_IPLR), ipl, summary);
 151     }
 152
 153 }
 154
 155 template <class CPU>
 156 void
 157 AlphaISA::zeroRegisters(CPU *cpu)
 158 {
 159     // Insure ISA semantics
 160     // (no longer very clean due to the change in setIntReg() in the
 161     // cpu model.  Consider changing later.)
 162     cpu->xc->setIntReg(ZeroReg, 0);
 163     cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
 164 }
 165
 166 void
 167 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 168 {
 169 /*    bool use_pc = (fault == NoFault);
 170
 171     if (fault->isA<ArithmeticFault>())
 172         panic("arithmetic faults NYI...");
 173
 174     // compute exception restart address
 175     if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
 176         // traps...  skip faulting instruction
 177         regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
 178     } else {
 179         // fault, post fault at excepting instruction
 180         regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
 181     }
 182
 183     // jump to expection address (PAL PC bit set here as well...)
 184     if (!use_pc)
 185         regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
 186             (dynamic_cast<AlphaFault *>(fault.get()))->vect();
 187     else
 188         regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
 189 */
 190     // that's it! (orders of magnitude less painful than x86)
 191 }
 192
 193 Fault
 194 ExecContext::hwrei()
 195 {
 196     if (!inPalMode())
 197         return new UnimplementedOpcodeFault;
 198
 199     setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
 200
 201     if (!misspeculating()) {
 202         kernelStats->hwrei();
 203
 204         if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
 205             AlphaISA::swap_palshadow(&regs, false);
 206
 207         cpu->checkInterrupts = true;
 208     }
 209
 210     // FIXME: XXX check for interrupts? XXX
 211     return NoFault;
 212 }
 213
 214 void
 215 AlphaISA::MiscRegFile::clearIprs()
 216 {
 217     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
 218 }
 219
 220 AlphaISA::MiscReg
 221 AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
 222 {
 223     uint64_t retval = 0;        // return value, default 0
 224
 225     switch (idx) {
 226       case AlphaISA::IPR_PALtemp0:
 227       case AlphaISA::IPR_PALtemp1:
 228       case AlphaISA::IPR_PALtemp2:
 229       case AlphaISA::IPR_PALtemp3:
 230       case AlphaISA::IPR_PALtemp4:
 231       case AlphaISA::IPR_PALtemp5:
 232       case AlphaISA::IPR_PALtemp6:
 233       case AlphaISA::IPR_PALtemp7:
 234       case AlphaISA::IPR_PALtemp8:
 235       case AlphaISA::IPR_PALtemp9:
 236       case AlphaISA::IPR_PALtemp10:
 237       case AlphaISA::IPR_PALtemp11:
 238       case AlphaISA::IPR_PALtemp12:
 239       case AlphaISA::IPR_PALtemp13:
 240       case AlphaISA::IPR_PALtemp14:
 241       case AlphaISA::IPR_PALtemp15:
 242       case AlphaISA::IPR_PALtemp16:
 243       case AlphaISA::IPR_PALtemp17:
 244       case AlphaISA::IPR_PALtemp18:
 245       case AlphaISA::IPR_PALtemp19:
 246       case AlphaISA::IPR_PALtemp20:
 247       case AlphaISA::IPR_PALtemp21:
 248       case AlphaISA::IPR_PALtemp22:
 249       case AlphaISA::IPR_PALtemp23:
 250       case AlphaISA::IPR_PAL_BASE:
 251
 252       case AlphaISA::IPR_IVPTBR:
 253       case AlphaISA::IPR_DC_MODE:
 254       case AlphaISA::IPR_MAF_MODE:
 255       case AlphaISA::IPR_ISR:
 256       case AlphaISA::IPR_EXC_ADDR:
 257       case AlphaISA::IPR_IC_PERR_STAT:
 258       case AlphaISA::IPR_DC_PERR_STAT:
 259       case AlphaISA::IPR_MCSR:
 260       case AlphaISA::IPR_ASTRR:
 261       case AlphaISA::IPR_ASTER:
 262       case AlphaISA::IPR_SIRR:
 263       case AlphaISA::IPR_ICSR:
 264       case AlphaISA::IPR_ICM:
 265       case AlphaISA::IPR_DTB_CM:
 266       case AlphaISA::IPR_IPLR:
 267       case AlphaISA::IPR_INTID:
 268       case AlphaISA::IPR_PMCTR:
 269         // no side-effect
 270         retval = ipr[idx];
 271         break;
 272
 273       case AlphaISA::IPR_CC:
 274         retval |= ipr[idx] & ULL(0xffffffff00000000);
 275         retval |= xc->cpu->curCycle()  & ULL(0x00000000ffffffff);
 276         break;
 277
 278       case AlphaISA::IPR_VA:
 279         retval = ipr[idx];
 280         break;
 281
 282       case AlphaISA::IPR_VA_FORM:
 283       case AlphaISA::IPR_MM_STAT:
 284       case AlphaISA::IPR_IFAULT_VA_FORM:
 285       case AlphaISA::IPR_EXC_MASK:
 286       case AlphaISA::IPR_EXC_SUM:
 287         retval = ipr[idx];
 288         break;
 289
 290       case AlphaISA::IPR_DTB_PTE:
 291         {
 292             AlphaISA::PTE &pte = xc->dtb->index(!xc->misspeculating());
 293
 294             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
 295             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
 296             retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
 297             retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
 298             retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
 299             retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
 300             retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
 301         }
 302         break;
 303
 304         // write only registers
 305       case AlphaISA::IPR_HWINT_CLR:
 306       case AlphaISA::IPR_SL_XMIT:
 307       case AlphaISA::IPR_DC_FLUSH:
 308       case AlphaISA::IPR_IC_FLUSH:
 309       case AlphaISA::IPR_ALT_MODE:
 310       case AlphaISA::IPR_DTB_IA:
 311       case AlphaISA::IPR_DTB_IAP:
 312       case AlphaISA::IPR_ITB_IA:
 313       case AlphaISA::IPR_ITB_IAP:
 314         fault = new UnimplementedOpcodeFault;
 315         break;
 316
 317       default:
 318         // invalid IPR
 319         fault = new UnimplementedOpcodeFault;
 320         break;
 321     }
 322
 323     return retval;
 324 }
 325
 326 #ifdef DEBUG
 327 // Cause the simulator to break when changing to the following IPL
 328 int break_ipl = -1;
 329 #endif
 330
 331 Fault
 332 AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
 333 {
 334     uint64_t old;
 335
 336     if (xc->misspeculating())
 337         return NoFault;
 338
 339     switch (idx) {
 340       case AlphaISA::IPR_PALtemp0:
 341       case AlphaISA::IPR_PALtemp1:
 342       case AlphaISA::IPR_PALtemp2:
 343       case AlphaISA::IPR_PALtemp3:
 344       case AlphaISA::IPR_PALtemp4:
 345       case AlphaISA::IPR_PALtemp5:
 346       case AlphaISA::IPR_PALtemp6:
 347       case AlphaISA::IPR_PALtemp7:
 348       case AlphaISA::IPR_PALtemp8:
 349       case AlphaISA::IPR_PALtemp9:
 350       case AlphaISA::IPR_PALtemp10:
 351       case AlphaISA::IPR_PALtemp11:
 352       case AlphaISA::IPR_PALtemp12:
 353       case AlphaISA::IPR_PALtemp13:
 354       case AlphaISA::IPR_PALtemp14:
 355       case AlphaISA::IPR_PALtemp15:
 356       case AlphaISA::IPR_PALtemp16:
 357       case AlphaISA::IPR_PALtemp17:
 358       case AlphaISA::IPR_PALtemp18:
 359       case AlphaISA::IPR_PALtemp19:
 360       case AlphaISA::IPR_PALtemp20:
 361       case AlphaISA::IPR_PALtemp21:
 362       case AlphaISA::IPR_PALtemp22:
 363       case AlphaISA::IPR_PAL_BASE:
 364       case AlphaISA::IPR_IC_PERR_STAT:
 365       case AlphaISA::IPR_DC_PERR_STAT:
 366       case AlphaISA::IPR_PMCTR:
 367         // write entire quad w/ no side-effect
 368         ipr[idx] = val;
 369         break;
 370
 371       case AlphaISA::IPR_CC_CTL:
 372         // This IPR resets the cycle counter.  We assume this only
 373         // happens once... let's verify that.
 374         assert(ipr[idx] == 0);
 375         ipr[idx] = 1;
 376         break;
 377
 378       case AlphaISA::IPR_CC:
 379         // This IPR only writes the upper 64 bits.  It's ok to write
 380         // all 64 here since we mask out the lower 32 in rpcc (see
 381         // isa_desc).
 382         ipr[idx] = val;
 383         break;
 384
 385       case AlphaISA::IPR_PALtemp23:
 386         // write entire quad w/ no side-effect
 387         old = ipr[idx];
 388         ipr[idx] = val;
 389         xc->kernelStats->context(old, val);
 390         break;
 391
 392       case AlphaISA::IPR_DTB_PTE:
 393         // write entire quad w/ no side-effect, tag is forthcoming
 394         ipr[idx] = val;
 395         break;
 396
 397       case AlphaISA::IPR_EXC_ADDR:
 398         // second least significant bit in PC is always zero
 399         ipr[idx] = val & ~2;
 400         break;
 401
 402       case AlphaISA::IPR_ASTRR:
 403       case AlphaISA::IPR_ASTER:
 404         // only write least significant four bits - privilege mask
 405         ipr[idx] = val & 0xf;
 406         break;
 407
 408       case AlphaISA::IPR_IPLR:
 409 #ifdef DEBUG
 410         if (break_ipl != -1 && break_ipl == (val & 0x1f))
 411             debug_break();
 412 #endif
 413
 414         // only write least significant five bits - interrupt level
 415         ipr[idx] = val & 0x1f;
 416         xc->kernelStats->swpipl(ipr[idx]);
 417         break;
 418
 419       case AlphaISA::IPR_DTB_CM:
 420         if (val & 0x18)
 421             xc->kernelStats->mode(Kernel::user);
 422         else
 423             xc->kernelStats->mode(Kernel::kernel);
 424
 425       case AlphaISA::IPR_ICM:
 426         // only write two mode bits - processor mode
 427         ipr[idx] = val & 0x18;
 428         break;
 429
 430       case AlphaISA::IPR_ALT_MODE:
 431         // only write two mode bits - processor mode
 432         ipr[idx] = val & 0x18;
 433         break;
 434
 435       case AlphaISA::IPR_MCSR:
 436         // more here after optimization...
 437         ipr[idx] = val;
 438         break;
 439
 440       case AlphaISA::IPR_SIRR:
 441         // only write software interrupt mask
 442         ipr[idx] = val & 0x7fff0;
 443         break;
 444
 445       case AlphaISA::IPR_ICSR:
 446         ipr[idx] = val & ULL(0xffffff0300);
 447         break;
 448
 449       case AlphaISA::IPR_IVPTBR:
 450       case AlphaISA::IPR_MVPTBR:
 451         ipr[idx] = val & ULL(0xffffffffc0000000);
 452         break;
 453
 454       case AlphaISA::IPR_DC_TEST_CTL:
 455         ipr[idx] = val & 0x1ffb;
 456         break;
 457
 458       case AlphaISA::IPR_DC_MODE:
 459       case AlphaISA::IPR_MAF_MODE:
 460         ipr[idx] = val & 0x3f;
 461         break;
 462
 463       case AlphaISA::IPR_ITB_ASN:
 464         ipr[idx] = val & 0x7f0;
 465         break;
 466
 467       case AlphaISA::IPR_DTB_ASN:
 468         ipr[idx] = val & ULL(0xfe00000000000000);
 469         break;
 470
 471       case AlphaISA::IPR_EXC_SUM:
 472       case AlphaISA::IPR_EXC_MASK:
 473         // any write to this register clears it
 474         ipr[idx] = 0;
 475         break;
 476
 477       case AlphaISA::IPR_INTID:
 478       case AlphaISA::IPR_SL_RCV:
 479       case AlphaISA::IPR_MM_STAT:
 480       case AlphaISA::IPR_ITB_PTE_TEMP:
 481       case AlphaISA::IPR_DTB_PTE_TEMP:
 482         // read-only registers
 483         return new UnimplementedOpcodeFault;
 484
 485       case AlphaISA::IPR_HWINT_CLR:
 486       case AlphaISA::IPR_SL_XMIT:
 487       case AlphaISA::IPR_DC_FLUSH:
 488       case AlphaISA::IPR_IC_FLUSH:
 489         // the following are write only
 490         ipr[idx] = val;
 491         break;
 492
 493       case AlphaISA::IPR_DTB_IA:
 494         // really a control write
 495         ipr[idx] = 0;
 496
 497         xc->dtb->flushAll();
 498         break;
 499
 500       case AlphaISA::IPR_DTB_IAP:
 501         // really a control write
 502         ipr[idx] = 0;
 503
 504         xc->dtb->flushProcesses();
 505         break;
 506
 507       case AlphaISA::IPR_DTB_IS:
 508         // really a control write
 509         ipr[idx] = val;
 510
 511         xc->dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
 512         break;
 513
 514       case AlphaISA::IPR_DTB_TAG: {
 515           struct AlphaISA::PTE pte;
 516
 517           // FIXME: granularity hints NYI...
 518           if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
 519               panic("PTE GH field != 0");
 520
 521           // write entire quad
 522           ipr[idx] = val;
 523
 524           // construct PTE for new entry
 525           pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
 526           pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
 527           pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
 528           pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
 529           pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
 530           pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
 531           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 532
 533           // insert new TAG/PTE value into data TLB
 534           xc->dtb->insert(val, pte);
 535       }
 536         break;
 537
 538       case AlphaISA::IPR_ITB_PTE: {
 539           struct AlphaISA::PTE pte;
 540
 541           // FIXME: granularity hints NYI...
 542           if (ITB_PTE_GH(val) != 0)
 543               panic("PTE GH field != 0");
 544
 545           // write entire quad
 546           ipr[idx] = val;
 547
 548           // construct PTE for new entry
 549           pte.ppn = ITB_PTE_PPN(val);
 550           pte.xre = ITB_PTE_XRE(val);
 551           pte.xwe = 0;
 552           pte.fonr = ITB_PTE_FONR(val);
 553           pte.fonw = ITB_PTE_FONW(val);
 554           pte.asma = ITB_PTE_ASMA(val);
 555           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 556
 557           // insert new TAG/PTE value into data TLB
 558           xc->itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
 559       }
 560         break;
 561
 562       case AlphaISA::IPR_ITB_IA:
 563         // really a control write
 564         ipr[idx] = 0;
 565
 566         xc->itb->flushAll();
 567         break;
 568
 569       case AlphaISA::IPR_ITB_IAP:
 570         // really a control write
 571         ipr[idx] = 0;
 572
 573         xc->itb->flushProcesses();
 574         break;
 575
 576       case AlphaISA::IPR_ITB_IS:
 577         // really a control write
 578         ipr[idx] = val;
 579
 580         xc->itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
 581         break;
 582
 583       default:
 584         // invalid IPR
 585         return new UnimplementedOpcodeFault;
 586     }
 587
 588     // no error...
 589     return NoFault;
 590 }
 591
 592 /**
 593  * Check for special simulator handling of specific PAL calls.
 594  * If return value is false, actual PAL call will be suppressed.
 595  */
 596 bool
 597 ExecContext::simPalCheck(int palFunc)
 598 {
 599     kernelStats->callpal(palFunc);
 600
 601     switch (palFunc) {
 602       case PAL::halt:
 603         halt();
 604         if (--System::numSystemsRunning == 0)
 605             new SimExitEvent("all cpus halted");
 606         break;
 607
 608       case PAL::bpt:
 609       case PAL::bugchk:
 610         if (system->breakpoint())
 611             return false;
 612         break;
 613     }
 614
 615     return true;
 616 }
 617
 618 //Forward instantiation for FastCPU object
 619 template
 620 void AlphaISA::processInterrupts(FastCPU *xc);
 621
 622 //Forward instantiation for FastCPU object
 623 template
 624 void AlphaISA::zeroRegisters(FastCPU *xc);
 625
 626 #endif // FULL_SYSTEM