3 #include "arch/alpha/alpha_memory.hh"
4 #include "arch/alpha/isa_traits.hh"
5 #include "arch/alpha/osfpal.hh"
7 #include "base/remote_gdb.hh"
8 #include "base/stats/events.hh"
9 #include "cpu/base_cpu.hh"
10 #include "cpu/exec_context.hh"
11 #include "cpu/fast_cpu/fast_cpu.hh"
12 #include "kern/kernel_stats.hh"
13 #include "sim/debug.hh"
14 #include "sim/sim_events.hh"
20 ////////////////////////////////////////////////////////////////////////
25 AlphaISA::swap_palshadow(RegFile
*regs
, bool use_shadow
)
27 if (regs
->pal_shadow
== use_shadow
)
28 panic("swap_palshadow: wrong PAL shadow state");
30 regs
->pal_shadow
= use_shadow
;
32 for (int i
= 0; i
< NumIntRegs
; i
++) {
34 IntReg temp
= regs
->intRegFile
[i
];
35 regs
->intRegFile
[i
] = regs
->palregs
[i
];
36 regs
->palregs
[i
] = temp
;
41 ////////////////////////////////////////////////////////////////////////
43 // Machine dependent functions
46 AlphaISA::initCPU(RegFile
*regs
)
49 // CPU comes up with PAL regs enabled
50 swap_palshadow(regs
, true);
52 regs
->pc
= regs
->ipr
[IPR_PAL_BASE
] + fault_addr
[Reset_Fault
];
53 regs
->npc
= regs
->pc
+ sizeof(MachInst
);
56 ////////////////////////////////////////////////////////////////////////
58 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
61 AlphaISA::fault_addr
[Num_Faults
] = {
62 0x0000, /* No_Fault */
63 0x0001, /* Reset_Fault */
64 0x0401, /* Machine_Check_Fault */
65 0x0501, /* Arithmetic_Fault */
66 0x0101, /* Interrupt_Fault */
67 0x0201, /* Ndtb_Miss_Fault */
68 0x0281, /* Pdtb_Miss_Fault */
69 0x0301, /* Alignment_Fault */
70 0x0381, /* DTB_Fault_Fault */
71 0x0381, /* DTB_Acv_Fault */
72 0x0181, /* ITB_Miss_Fault */
73 0x0181, /* ITB_Fault_Fault */
74 0x0081, /* ITB_Acv_Fault */
75 0x0481, /* Unimplemented_Opcode_Fault */
76 0x0581, /* Fen_Fault */
77 0x2001, /* Pal_Fault */
78 0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
81 const int AlphaISA::reg_redir
[AlphaISA::NumIntRegs
] = {
82 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
83 /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
84 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
85 /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
87 ////////////////////////////////////////////////////////////////////////
92 AlphaISA::initIPRs(RegFile
*regs
)
94 uint64_t *ipr
= regs
->ipr
;
96 bzero((char *)ipr
, NumInternalProcRegs
* sizeof(InternalProcReg
));
97 ipr
[IPR_PAL_BASE
] = PalBase
;
104 AlphaISA::processInterrupts(CPU
*cpu
)
106 //Check if there are any outstanding interrupts
107 //Handle the interrupts
110 IntReg
*ipr
= cpu
->getIprPtr();
112 cpu
->checkInterrupts
= false;
115 panic("asynchronous traps not implemented\n");
118 for (int i
= INTLEVEL_SOFTWARE_MIN
;
119 i
< INTLEVEL_SOFTWARE_MAX
; i
++) {
120 if (ipr
[IPR_SIRR
] & (ULL(1) << i
)) {
121 // See table 4-19 of the 21164 hardware reference
122 ipl
= (i
- INTLEVEL_SOFTWARE_MIN
) + 1;
123 summary
|= (ULL(1) << i
);
128 uint64_t interrupts
= cpu
->intr_status();
131 for (int i
= INTLEVEL_EXTERNAL_MIN
;
132 i
< INTLEVEL_EXTERNAL_MAX
; i
++) {
133 if (interrupts
& (ULL(1) << i
)) {
134 // See table 4-19 of the 21164 hardware reference
136 summary
|= (ULL(1) << i
);
141 if (ipl
&& ipl
> ipr
[IPR_IPLR
]) {
142 ipr
[IPR_ISR
] = summary
;
143 ipr
[IPR_INTID
] = ipl
;
144 cpu
->trap(Interrupt_Fault
);
145 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
146 ipr
[IPR_IPLR
], ipl
, summary
);
153 AlphaISA::zeroRegisters(CPU
*cpu
)
155 // Insure ISA semantics
156 // (no longer very clean due to the change in setIntReg() in the
157 // cpu model. Consider changing later.)
158 cpu
->xc
->setIntReg(ZeroReg
, 0);
159 cpu
->xc
->setFloatRegDouble(ZeroReg
, 0.0);
163 ExecContext::ev5_trap(Fault fault
)
165 DPRINTF(Fault
, "Fault %s at PC: %#x\n", FaultName(fault
), regs
.pc
);
166 cpu
->recordEvent(csprintf("Fault %s", FaultName(fault
)));
168 assert(!misspeculating());
169 kernelStats
->fault(fault
);
171 if (fault
== Arithmetic_Fault
)
172 panic("Arithmetic traps are unimplemented!");
174 AlphaISA::InternalProcReg
*ipr
= regs
.ipr
;
176 // exception restart address
177 if (fault
!= Interrupt_Fault
|| !inPalMode())
178 ipr
[AlphaISA::IPR_EXC_ADDR
] = regs
.pc
;
180 if (fault
== Pal_Fault
|| fault
== Arithmetic_Fault
/* ||
181 fault == Interrupt_Fault && !inPalMode() */) {
182 // traps... skip faulting instruction
183 ipr
[AlphaISA::IPR_EXC_ADDR
] += 4;
187 AlphaISA::swap_palshadow(®s
, true);
189 regs
.pc
= ipr
[AlphaISA::IPR_PAL_BASE
] + AlphaISA::fault_addr
[fault
];
190 regs
.npc
= regs
.pc
+ sizeof(MachInst
);
195 AlphaISA::intr_post(RegFile
*regs
, Fault fault
, Addr pc
)
197 InternalProcReg
*ipr
= regs
->ipr
;
198 bool use_pc
= (fault
== No_Fault
);
200 if (fault
== Arithmetic_Fault
)
201 panic("arithmetic faults NYI...");
203 // compute exception restart address
204 if (use_pc
|| fault
== Pal_Fault
|| fault
== Arithmetic_Fault
) {
205 // traps... skip faulting instruction
206 ipr
[IPR_EXC_ADDR
] = regs
->pc
+ 4;
208 // fault, post fault at excepting instruction
209 ipr
[IPR_EXC_ADDR
] = regs
->pc
;
212 // jump to expection address (PAL PC bit set here as well...)
214 regs
->npc
= ipr
[IPR_PAL_BASE
] + fault_addr
[fault
];
216 regs
->npc
= ipr
[IPR_PAL_BASE
] + pc
;
218 // that's it! (orders of magnitude less painful than x86)
224 uint64_t *ipr
= regs
.ipr
;
227 return Unimplemented_Opcode_Fault
;
229 setNextPC(ipr
[AlphaISA::IPR_EXC_ADDR
]);
231 if (!misspeculating()) {
232 kernelStats
->hwrei();
234 if ((ipr
[AlphaISA::IPR_EXC_ADDR
] & 1) == 0)
235 AlphaISA::swap_palshadow(®s
, false);
237 cpu
->checkInterrupts
= true;
240 // FIXME: XXX check for interrupts? XXX
245 ExecContext::readIpr(int idx
, Fault
&fault
)
247 uint64_t *ipr
= regs
.ipr
;
248 uint64_t retval
= 0; // return value, default 0
251 case AlphaISA::IPR_PALtemp0
:
252 case AlphaISA::IPR_PALtemp1
:
253 case AlphaISA::IPR_PALtemp2
:
254 case AlphaISA::IPR_PALtemp3
:
255 case AlphaISA::IPR_PALtemp4
:
256 case AlphaISA::IPR_PALtemp5
:
257 case AlphaISA::IPR_PALtemp6
:
258 case AlphaISA::IPR_PALtemp7
:
259 case AlphaISA::IPR_PALtemp8
:
260 case AlphaISA::IPR_PALtemp9
:
261 case AlphaISA::IPR_PALtemp10
:
262 case AlphaISA::IPR_PALtemp11
:
263 case AlphaISA::IPR_PALtemp12
:
264 case AlphaISA::IPR_PALtemp13
:
265 case AlphaISA::IPR_PALtemp14
:
266 case AlphaISA::IPR_PALtemp15
:
267 case AlphaISA::IPR_PALtemp16
:
268 case AlphaISA::IPR_PALtemp17
:
269 case AlphaISA::IPR_PALtemp18
:
270 case AlphaISA::IPR_PALtemp19
:
271 case AlphaISA::IPR_PALtemp20
:
272 case AlphaISA::IPR_PALtemp21
:
273 case AlphaISA::IPR_PALtemp22
:
274 case AlphaISA::IPR_PALtemp23
:
275 case AlphaISA::IPR_PAL_BASE
:
277 case AlphaISA::IPR_IVPTBR
:
278 case AlphaISA::IPR_DC_MODE
:
279 case AlphaISA::IPR_MAF_MODE
:
280 case AlphaISA::IPR_ISR
:
281 case AlphaISA::IPR_EXC_ADDR
:
282 case AlphaISA::IPR_IC_PERR_STAT
:
283 case AlphaISA::IPR_DC_PERR_STAT
:
284 case AlphaISA::IPR_MCSR
:
285 case AlphaISA::IPR_ASTRR
:
286 case AlphaISA::IPR_ASTER
:
287 case AlphaISA::IPR_SIRR
:
288 case AlphaISA::IPR_ICSR
:
289 case AlphaISA::IPR_ICM
:
290 case AlphaISA::IPR_DTB_CM
:
291 case AlphaISA::IPR_IPLR
:
292 case AlphaISA::IPR_INTID
:
293 case AlphaISA::IPR_PMCTR
:
298 case AlphaISA::IPR_CC
:
299 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
300 retval
|= cpu
->curCycle() & ULL(0x00000000ffffffff);
303 case AlphaISA::IPR_VA
:
307 case AlphaISA::IPR_VA_FORM
:
308 case AlphaISA::IPR_MM_STAT
:
309 case AlphaISA::IPR_IFAULT_VA_FORM
:
310 case AlphaISA::IPR_EXC_MASK
:
311 case AlphaISA::IPR_EXC_SUM
:
315 case AlphaISA::IPR_DTB_PTE
:
317 AlphaISA::PTE
&pte
= dtb
->index(!misspeculating());
319 retval
|= ((u_int64_t
)pte
.ppn
& ULL(0x7ffffff)) << 32;
320 retval
|= ((u_int64_t
)pte
.xre
& ULL(0xf)) << 8;
321 retval
|= ((u_int64_t
)pte
.xwe
& ULL(0xf)) << 12;
322 retval
|= ((u_int64_t
)pte
.fonr
& ULL(0x1)) << 1;
323 retval
|= ((u_int64_t
)pte
.fonw
& ULL(0x1))<< 2;
324 retval
|= ((u_int64_t
)pte
.asma
& ULL(0x1)) << 4;
325 retval
|= ((u_int64_t
)pte
.asn
& ULL(0x7f)) << 57;
329 // write only registers
330 case AlphaISA::IPR_HWINT_CLR
:
331 case AlphaISA::IPR_SL_XMIT
:
332 case AlphaISA::IPR_DC_FLUSH
:
333 case AlphaISA::IPR_IC_FLUSH
:
334 case AlphaISA::IPR_ALT_MODE
:
335 case AlphaISA::IPR_DTB_IA
:
336 case AlphaISA::IPR_DTB_IAP
:
337 case AlphaISA::IPR_ITB_IA
:
338 case AlphaISA::IPR_ITB_IAP
:
339 fault
= Unimplemented_Opcode_Fault
;
344 fault
= Unimplemented_Opcode_Fault
;
352 // Cause the simulator to break when changing to the following IPL
357 ExecContext::setIpr(int idx
, uint64_t val
)
359 uint64_t *ipr
= regs
.ipr
;
362 if (misspeculating())
366 case AlphaISA::IPR_PALtemp0
:
367 case AlphaISA::IPR_PALtemp1
:
368 case AlphaISA::IPR_PALtemp2
:
369 case AlphaISA::IPR_PALtemp3
:
370 case AlphaISA::IPR_PALtemp4
:
371 case AlphaISA::IPR_PALtemp5
:
372 case AlphaISA::IPR_PALtemp6
:
373 case AlphaISA::IPR_PALtemp7
:
374 case AlphaISA::IPR_PALtemp8
:
375 case AlphaISA::IPR_PALtemp9
:
376 case AlphaISA::IPR_PALtemp10
:
377 case AlphaISA::IPR_PALtemp11
:
378 case AlphaISA::IPR_PALtemp12
:
379 case AlphaISA::IPR_PALtemp13
:
380 case AlphaISA::IPR_PALtemp14
:
381 case AlphaISA::IPR_PALtemp15
:
382 case AlphaISA::IPR_PALtemp16
:
383 case AlphaISA::IPR_PALtemp17
:
384 case AlphaISA::IPR_PALtemp18
:
385 case AlphaISA::IPR_PALtemp19
:
386 case AlphaISA::IPR_PALtemp20
:
387 case AlphaISA::IPR_PALtemp21
:
388 case AlphaISA::IPR_PALtemp22
:
389 case AlphaISA::IPR_PAL_BASE
:
390 case AlphaISA::IPR_IC_PERR_STAT
:
391 case AlphaISA::IPR_DC_PERR_STAT
:
392 case AlphaISA::IPR_PMCTR
:
393 // write entire quad w/ no side-effect
397 case AlphaISA::IPR_CC_CTL
:
398 // This IPR resets the cycle counter. We assume this only
399 // happens once... let's verify that.
400 assert(ipr
[idx
] == 0);
404 case AlphaISA::IPR_CC
:
405 // This IPR only writes the upper 64 bits. It's ok to write
406 // all 64 here since we mask out the lower 32 in rpcc (see
411 case AlphaISA::IPR_PALtemp23
:
412 // write entire quad w/ no side-effect
415 kernelStats
->context(old
, val
);
418 case AlphaISA::IPR_DTB_PTE
:
419 // write entire quad w/ no side-effect, tag is forthcoming
423 case AlphaISA::IPR_EXC_ADDR
:
424 // second least significant bit in PC is always zero
428 case AlphaISA::IPR_ASTRR
:
429 case AlphaISA::IPR_ASTER
:
430 // only write least significant four bits - privilege mask
431 ipr
[idx
] = val
& 0xf;
434 case AlphaISA::IPR_IPLR
:
436 if (break_ipl
!= -1 && break_ipl
== (val
& 0x1f))
440 // only write least significant five bits - interrupt level
441 ipr
[idx
] = val
& 0x1f;
442 kernelStats
->swpipl(ipr
[idx
]);
445 case AlphaISA::IPR_DTB_CM
:
447 kernelStats
->mode(Kernel::user
);
449 kernelStats
->mode(Kernel::kernel
);
451 case AlphaISA::IPR_ICM
:
452 // only write two mode bits - processor mode
453 ipr
[idx
] = val
& 0x18;
456 case AlphaISA::IPR_ALT_MODE
:
457 // only write two mode bits - processor mode
458 ipr
[idx
] = val
& 0x18;
461 case AlphaISA::IPR_MCSR
:
462 // more here after optimization...
466 case AlphaISA::IPR_SIRR
:
467 // only write software interrupt mask
468 ipr
[idx
] = val
& 0x7fff0;
471 case AlphaISA::IPR_ICSR
:
472 ipr
[idx
] = val
& ULL(0xffffff0300);
475 case AlphaISA::IPR_IVPTBR
:
476 case AlphaISA::IPR_MVPTBR
:
477 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
480 case AlphaISA::IPR_DC_TEST_CTL
:
481 ipr
[idx
] = val
& 0x1ffb;
484 case AlphaISA::IPR_DC_MODE
:
485 case AlphaISA::IPR_MAF_MODE
:
486 ipr
[idx
] = val
& 0x3f;
489 case AlphaISA::IPR_ITB_ASN
:
490 ipr
[idx
] = val
& 0x7f0;
493 case AlphaISA::IPR_DTB_ASN
:
494 ipr
[idx
] = val
& ULL(0xfe00000000000000);
497 case AlphaISA::IPR_EXC_SUM
:
498 case AlphaISA::IPR_EXC_MASK
:
499 // any write to this register clears it
503 case AlphaISA::IPR_INTID
:
504 case AlphaISA::IPR_SL_RCV
:
505 case AlphaISA::IPR_MM_STAT
:
506 case AlphaISA::IPR_ITB_PTE_TEMP
:
507 case AlphaISA::IPR_DTB_PTE_TEMP
:
508 // read-only registers
509 return Unimplemented_Opcode_Fault
;
511 case AlphaISA::IPR_HWINT_CLR
:
512 case AlphaISA::IPR_SL_XMIT
:
513 case AlphaISA::IPR_DC_FLUSH
:
514 case AlphaISA::IPR_IC_FLUSH
:
515 // the following are write only
519 case AlphaISA::IPR_DTB_IA
:
520 // really a control write
526 case AlphaISA::IPR_DTB_IAP
:
527 // really a control write
530 dtb
->flushProcesses();
533 case AlphaISA::IPR_DTB_IS
:
534 // really a control write
537 dtb
->flushAddr(val
, DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
540 case AlphaISA::IPR_DTB_TAG
: {
541 struct AlphaISA::PTE pte
;
543 // FIXME: granularity hints NYI...
544 if (DTB_PTE_GH(ipr
[AlphaISA::IPR_DTB_PTE
]) != 0)
545 panic("PTE GH field != 0");
550 // construct PTE for new entry
551 pte
.ppn
= DTB_PTE_PPN(ipr
[AlphaISA::IPR_DTB_PTE
]);
552 pte
.xre
= DTB_PTE_XRE(ipr
[AlphaISA::IPR_DTB_PTE
]);
553 pte
.xwe
= DTB_PTE_XWE(ipr
[AlphaISA::IPR_DTB_PTE
]);
554 pte
.fonr
= DTB_PTE_FONR(ipr
[AlphaISA::IPR_DTB_PTE
]);
555 pte
.fonw
= DTB_PTE_FONW(ipr
[AlphaISA::IPR_DTB_PTE
]);
556 pte
.asma
= DTB_PTE_ASMA(ipr
[AlphaISA::IPR_DTB_PTE
]);
557 pte
.asn
= DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]);
559 // insert new TAG/PTE value into data TLB
560 dtb
->insert(val
, pte
);
564 case AlphaISA::IPR_ITB_PTE
: {
565 struct AlphaISA::PTE pte
;
567 // FIXME: granularity hints NYI...
568 if (ITB_PTE_GH(val
) != 0)
569 panic("PTE GH field != 0");
574 // construct PTE for new entry
575 pte
.ppn
= ITB_PTE_PPN(val
);
576 pte
.xre
= ITB_PTE_XRE(val
);
578 pte
.fonr
= ITB_PTE_FONR(val
);
579 pte
.fonw
= ITB_PTE_FONW(val
);
580 pte
.asma
= ITB_PTE_ASMA(val
);
581 pte
.asn
= ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]);
583 // insert new TAG/PTE value into data TLB
584 itb
->insert(ipr
[AlphaISA::IPR_ITB_TAG
], pte
);
588 case AlphaISA::IPR_ITB_IA
:
589 // really a control write
595 case AlphaISA::IPR_ITB_IAP
:
596 // really a control write
599 itb
->flushProcesses();
602 case AlphaISA::IPR_ITB_IS
:
603 // really a control write
606 itb
->flushAddr(val
, ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]));
611 return Unimplemented_Opcode_Fault
;
619 * Check for special simulator handling of specific PAL calls.
620 * If return value is false, actual PAL call will be suppressed.
623 ExecContext::simPalCheck(int palFunc
)
625 kernelStats
->callpal(palFunc
);
630 if (--System::numSystemsRunning
== 0)
631 new SimExitEvent("all cpus halted");
636 if (system
->breakpoint())
644 //Forward instantiation for FastCPU object
646 void AlphaISA::processInterrupts(FastCPU
*xc
);
648 //Forward instantiation for FastCPU object
650 void AlphaISA::zeroRegisters(FastCPU
*xc
);
652 #endif // FULL_SYSTEM