arch/alpha/ev5.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/alpha/alpha_memory.hh"
  30 #include "arch/alpha/isa_traits.hh"
  31 #include "arch/alpha/osfpal.hh"
  32 #include "base/kgdb.h"
  33 #include "base/remote_gdb.hh"
  34 #include "base/stats/events.hh"
  35 #include "config/full_system.hh"
  36 #include "cpu/base.hh"
  37 #include "cpu/exec_context.hh"
  38 #include "cpu/fast/cpu.hh"
  39 #include "kern/kernel_stats.hh"
  40 #include "sim/debug.hh"
  41 #include "sim/sim_events.hh"
  42
  43 #if FULL_SYSTEM
  44
  45 using namespace EV5;
  46
  47 ////////////////////////////////////////////////////////////////////////
  48 //
  49 //
  50 //
  51 void
  52 AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
  53 {
  54     if (regs->pal_shadow == use_shadow)
  55         panic("swap_palshadow: wrong PAL shadow state");
  56
  57     regs->pal_shadow = use_shadow;
  58
  59     for (int i = 0; i < NumIntRegs; i++) {
  60         if (reg_redir[i]) {
  61             IntReg temp = regs->intRegFile[i];
  62             regs->intRegFile[i] = regs->palregs[i];
  63             regs->palregs[i] = temp;
  64         }
  65     }
  66 }
  67
  68 ////////////////////////////////////////////////////////////////////////
  69 //
  70 //  Machine dependent functions
  71 //
  72 void
  73 AlphaISA::initCPU(RegFile *regs)
  74 {
  75     initIPRs(regs);
  76     // CPU comes up with PAL regs enabled
  77     swap_palshadow(regs, true);
  78
  79     regs->pc = regs->ipr[IPR_PAL_BASE] + (new ResetFault)->vect();
  80     regs->npc = regs->pc + sizeof(MachInst);
  81 }
  82
  83 ////////////////////////////////////////////////////////////////////////
  84 //
  85 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
  86 //
  87 const Addr
  88 AlphaISA::fault_addr(Fault fault)
  89 {
  90         //Check for the system wide faults
  91         if(fault == NoFault) return 0x0000;
  92         else if(fault->isA<MachineCheckFault>()) return 0x0401;
  93         else if(fault->isA<AlignmentFault>()) return 0x0301;
  94         //Deal with the alpha specific faults
  95         return ((AlphaFault *)(fault.get()))->vect();
  96 };
  97
  98 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
  99     /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
 100     /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
 101     /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
 102     /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
 103
 104 ////////////////////////////////////////////////////////////////////////
 105 //
 106 //
 107 //
 108 void
 109 AlphaISA::initIPRs(RegFile *regs)
 110 {
 111     uint64_t *ipr = regs->ipr;
 112
 113     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
 114     ipr[IPR_PAL_BASE] = PalBase;
 115     ipr[IPR_MCSR] = 0x6;
 116 }
 117
 118
 119 template <class CPU>
 120 void
 121 AlphaISA::processInterrupts(CPU *cpu)
 122 {
 123     //Check if there are any outstanding interrupts
 124     //Handle the interrupts
 125     int ipl = 0;
 126     int summary = 0;
 127     IntReg *ipr = cpu->getIprPtr();
 128
 129     cpu->checkInterrupts = false;
 130
 131     if (ipr[IPR_ASTRR])
 132         panic("asynchronous traps not implemented\n");
 133
 134     if (ipr[IPR_SIRR]) {
 135         for (int i = INTLEVEL_SOFTWARE_MIN;
 136              i < INTLEVEL_SOFTWARE_MAX; i++) {
 137             if (ipr[IPR_SIRR] & (ULL(1) << i)) {
 138                 // See table 4-19 of the 21164 hardware reference
 139                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
 140                 summary |= (ULL(1) << i);
 141             }
 142         }
 143     }
 144
 145     uint64_t interrupts = cpu->intr_status();
 146
 147     if (interrupts) {
 148         for (int i = INTLEVEL_EXTERNAL_MIN;
 149              i < INTLEVEL_EXTERNAL_MAX; i++) {
 150             if (interrupts & (ULL(1) << i)) {
 151                 // See table 4-19 of the 21164 hardware reference
 152                 ipl = i;
 153                 summary |= (ULL(1) << i);
 154             }
 155         }
 156     }
 157
 158     if (ipl && ipl > ipr[IPR_IPLR]) {
 159         ipr[IPR_ISR] = summary;
 160         ipr[IPR_INTID] = ipl;
 161         cpu->trap(new InterruptFault);
 162         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 163                 ipr[IPR_IPLR], ipl, summary);
 164     }
 165
 166 }
 167
 168 template <class CPU>
 169 void
 170 AlphaISA::zeroRegisters(CPU *cpu)
 171 {
 172     // Insure ISA semantics
 173     // (no longer very clean due to the change in setIntReg() in the
 174     // cpu model.  Consider changing later.)
 175     cpu->xc->setIntReg(ZeroReg, 0);
 176     cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
 177 }
 178
 179 void
 180 ExecContext::ev5_trap(Fault fault)
 181 {
 182     DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
 183     cpu->recordEvent(csprintf("Fault %s", fault->name()));
 184
 185     assert(!misspeculating());
 186     kernelStats->fault(fault);
 187
 188     if (fault->isA<ArithmeticFault>())
 189         panic("Arithmetic traps are unimplemented!");
 190
 191     AlphaISA::InternalProcReg *ipr = regs.ipr;
 192
 193     // exception restart address
 194     if (!fault->isA<InterruptFault>() || !inPalMode())
 195         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 196
 197     if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
 198         fault == InterruptFault && !inPalMode() */) {
 199         // traps...  skip faulting instruction
 200         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
 201     }
 202
 203     if (!inPalMode())
 204         AlphaISA::swap_palshadow(&regs, true);
 205
 206     regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
 207     regs.npc = regs.pc + sizeof(MachInst);
 208 }
 209
 210
 211 void
 212 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 213 {
 214     InternalProcReg *ipr = regs->ipr;
 215     bool use_pc = (fault == NoFault);
 216
 217     if (fault->isA<ArithmeticFault>())
 218         panic("arithmetic faults NYI...");
 219
 220     // compute exception restart address
 221     if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
 222         // traps...  skip faulting instruction
 223         ipr[IPR_EXC_ADDR] = regs->pc + 4;
 224     } else {
 225         // fault, post fault at excepting instruction
 226         ipr[IPR_EXC_ADDR] = regs->pc;
 227     }
 228
 229     // jump to expection address (PAL PC bit set here as well...)
 230     if (!use_pc)
 231         regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
 232     else
 233         regs->npc = ipr[IPR_PAL_BASE] + pc;
 234
 235     // that's it! (orders of magnitude less painful than x86)
 236 }
 237
 238 Fault
 239 ExecContext::hwrei()
 240 {
 241     uint64_t *ipr = regs.ipr;
 242
 243     if (!inPalMode())
 244         return new UnimplementedOpcodeFault;
 245
 246     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 247
 248     if (!misspeculating()) {
 249         kernelStats->hwrei();
 250
 251         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
 252             AlphaISA::swap_palshadow(&regs, false);
 253
 254         cpu->checkInterrupts = true;
 255     }
 256
 257     // FIXME: XXX check for interrupts? XXX
 258     return NoFault;
 259 }
 260
 261 uint64_t
 262 ExecContext::readIpr(int idx, Fault &fault)
 263 {
 264     uint64_t *ipr = regs.ipr;
 265     uint64_t retval = 0;        // return value, default 0
 266
 267     switch (idx) {
 268       case AlphaISA::IPR_PALtemp0:
 269       case AlphaISA::IPR_PALtemp1:
 270       case AlphaISA::IPR_PALtemp2:
 271       case AlphaISA::IPR_PALtemp3:
 272       case AlphaISA::IPR_PALtemp4:
 273       case AlphaISA::IPR_PALtemp5:
 274       case AlphaISA::IPR_PALtemp6:
 275       case AlphaISA::IPR_PALtemp7:
 276       case AlphaISA::IPR_PALtemp8:
 277       case AlphaISA::IPR_PALtemp9:
 278       case AlphaISA::IPR_PALtemp10:
 279       case AlphaISA::IPR_PALtemp11:
 280       case AlphaISA::IPR_PALtemp12:
 281       case AlphaISA::IPR_PALtemp13:
 282       case AlphaISA::IPR_PALtemp14:
 283       case AlphaISA::IPR_PALtemp15:
 284       case AlphaISA::IPR_PALtemp16:
 285       case AlphaISA::IPR_PALtemp17:
 286       case AlphaISA::IPR_PALtemp18:
 287       case AlphaISA::IPR_PALtemp19:
 288       case AlphaISA::IPR_PALtemp20:
 289       case AlphaISA::IPR_PALtemp21:
 290       case AlphaISA::IPR_PALtemp22:
 291       case AlphaISA::IPR_PALtemp23:
 292       case AlphaISA::IPR_PAL_BASE:
 293
 294       case AlphaISA::IPR_IVPTBR:
 295       case AlphaISA::IPR_DC_MODE:
 296       case AlphaISA::IPR_MAF_MODE:
 297       case AlphaISA::IPR_ISR:
 298       case AlphaISA::IPR_EXC_ADDR:
 299       case AlphaISA::IPR_IC_PERR_STAT:
 300       case AlphaISA::IPR_DC_PERR_STAT:
 301       case AlphaISA::IPR_MCSR:
 302       case AlphaISA::IPR_ASTRR:
 303       case AlphaISA::IPR_ASTER:
 304       case AlphaISA::IPR_SIRR:
 305       case AlphaISA::IPR_ICSR:
 306       case AlphaISA::IPR_ICM:
 307       case AlphaISA::IPR_DTB_CM:
 308       case AlphaISA::IPR_IPLR:
 309       case AlphaISA::IPR_INTID:
 310       case AlphaISA::IPR_PMCTR:
 311         // no side-effect
 312         retval = ipr[idx];
 313         break;
 314
 315       case AlphaISA::IPR_CC:
 316         retval |= ipr[idx] & ULL(0xffffffff00000000);
 317         retval |= cpu->curCycle()  & ULL(0x00000000ffffffff);
 318         break;
 319
 320       case AlphaISA::IPR_VA:
 321         retval = ipr[idx];
 322         break;
 323
 324       case AlphaISA::IPR_VA_FORM:
 325       case AlphaISA::IPR_MM_STAT:
 326       case AlphaISA::IPR_IFAULT_VA_FORM:
 327       case AlphaISA::IPR_EXC_MASK:
 328       case AlphaISA::IPR_EXC_SUM:
 329         retval = ipr[idx];
 330         break;
 331
 332       case AlphaISA::IPR_DTB_PTE:
 333         {
 334             AlphaISA::PTE &pte = dtb->index(!misspeculating());
 335
 336             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
 337             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
 338             retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
 339             retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
 340             retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
 341             retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
 342             retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
 343         }
 344         break;
 345
 346         // write only registers
 347       case AlphaISA::IPR_HWINT_CLR:
 348       case AlphaISA::IPR_SL_XMIT:
 349       case AlphaISA::IPR_DC_FLUSH:
 350       case AlphaISA::IPR_IC_FLUSH:
 351       case AlphaISA::IPR_ALT_MODE:
 352       case AlphaISA::IPR_DTB_IA:
 353       case AlphaISA::IPR_DTB_IAP:
 354       case AlphaISA::IPR_ITB_IA:
 355       case AlphaISA::IPR_ITB_IAP:
 356         fault = new UnimplementedOpcodeFault;
 357         break;
 358
 359       default:
 360         // invalid IPR
 361         fault = new UnimplementedOpcodeFault;
 362         break;
 363     }
 364
 365     return retval;
 366 }
 367
 368 #ifdef DEBUG
 369 // Cause the simulator to break when changing to the following IPL
 370 int break_ipl = -1;
 371 #endif
 372
 373 Fault
 374 ExecContext::setIpr(int idx, uint64_t val)
 375 {
 376     uint64_t *ipr = regs.ipr;
 377     uint64_t old;
 378
 379     if (misspeculating())
 380         return NoFault;
 381
 382     switch (idx) {
 383       case AlphaISA::IPR_PALtemp0:
 384       case AlphaISA::IPR_PALtemp1:
 385       case AlphaISA::IPR_PALtemp2:
 386       case AlphaISA::IPR_PALtemp3:
 387       case AlphaISA::IPR_PALtemp4:
 388       case AlphaISA::IPR_PALtemp5:
 389       case AlphaISA::IPR_PALtemp6:
 390       case AlphaISA::IPR_PALtemp7:
 391       case AlphaISA::IPR_PALtemp8:
 392       case AlphaISA::IPR_PALtemp9:
 393       case AlphaISA::IPR_PALtemp10:
 394       case AlphaISA::IPR_PALtemp11:
 395       case AlphaISA::IPR_PALtemp12:
 396       case AlphaISA::IPR_PALtemp13:
 397       case AlphaISA::IPR_PALtemp14:
 398       case AlphaISA::IPR_PALtemp15:
 399       case AlphaISA::IPR_PALtemp16:
 400       case AlphaISA::IPR_PALtemp17:
 401       case AlphaISA::IPR_PALtemp18:
 402       case AlphaISA::IPR_PALtemp19:
 403       case AlphaISA::IPR_PALtemp20:
 404       case AlphaISA::IPR_PALtemp21:
 405       case AlphaISA::IPR_PALtemp22:
 406       case AlphaISA::IPR_PAL_BASE:
 407       case AlphaISA::IPR_IC_PERR_STAT:
 408       case AlphaISA::IPR_DC_PERR_STAT:
 409       case AlphaISA::IPR_PMCTR:
 410         // write entire quad w/ no side-effect
 411         ipr[idx] = val;
 412         break;
 413
 414       case AlphaISA::IPR_CC_CTL:
 415         // This IPR resets the cycle counter.  We assume this only
 416         // happens once... let's verify that.
 417         assert(ipr[idx] == 0);
 418         ipr[idx] = 1;
 419         break;
 420
 421       case AlphaISA::IPR_CC:
 422         // This IPR only writes the upper 64 bits.  It's ok to write
 423         // all 64 here since we mask out the lower 32 in rpcc (see
 424         // isa_desc).
 425         ipr[idx] = val;
 426         break;
 427
 428       case AlphaISA::IPR_PALtemp23:
 429         // write entire quad w/ no side-effect
 430         old = ipr[idx];
 431         ipr[idx] = val;
 432         kernelStats->context(old, val);
 433         break;
 434
 435       case AlphaISA::IPR_DTB_PTE:
 436         // write entire quad w/ no side-effect, tag is forthcoming
 437         ipr[idx] = val;
 438         break;
 439
 440       case AlphaISA::IPR_EXC_ADDR:
 441         // second least significant bit in PC is always zero
 442         ipr[idx] = val & ~2;
 443         break;
 444
 445       case AlphaISA::IPR_ASTRR:
 446       case AlphaISA::IPR_ASTER:
 447         // only write least significant four bits - privilege mask
 448         ipr[idx] = val & 0xf;
 449         break;
 450
 451       case AlphaISA::IPR_IPLR:
 452 #ifdef DEBUG
 453         if (break_ipl != -1 && break_ipl == (val & 0x1f))
 454             debug_break();
 455 #endif
 456
 457         // only write least significant five bits - interrupt level
 458         ipr[idx] = val & 0x1f;
 459         kernelStats->swpipl(ipr[idx]);
 460         break;
 461
 462       case AlphaISA::IPR_DTB_CM:
 463         if (val & 0x18)
 464             kernelStats->mode(Kernel::user);
 465         else
 466             kernelStats->mode(Kernel::kernel);
 467
 468       case AlphaISA::IPR_ICM:
 469         // only write two mode bits - processor mode
 470         ipr[idx] = val & 0x18;
 471         break;
 472
 473       case AlphaISA::IPR_ALT_MODE:
 474         // only write two mode bits - processor mode
 475         ipr[idx] = val & 0x18;
 476         break;
 477
 478       case AlphaISA::IPR_MCSR:
 479         // more here after optimization...
 480         ipr[idx] = val;
 481         break;
 482
 483       case AlphaISA::IPR_SIRR:
 484         // only write software interrupt mask
 485         ipr[idx] = val & 0x7fff0;
 486         break;
 487
 488       case AlphaISA::IPR_ICSR:
 489         ipr[idx] = val & ULL(0xffffff0300);
 490         break;
 491
 492       case AlphaISA::IPR_IVPTBR:
 493       case AlphaISA::IPR_MVPTBR:
 494         ipr[idx] = val & ULL(0xffffffffc0000000);
 495         break;
 496
 497       case AlphaISA::IPR_DC_TEST_CTL:
 498         ipr[idx] = val & 0x1ffb;
 499         break;
 500
 501       case AlphaISA::IPR_DC_MODE:
 502       case AlphaISA::IPR_MAF_MODE:
 503         ipr[idx] = val & 0x3f;
 504         break;
 505
 506       case AlphaISA::IPR_ITB_ASN:
 507         ipr[idx] = val & 0x7f0;
 508         break;
 509
 510       case AlphaISA::IPR_DTB_ASN:
 511         ipr[idx] = val & ULL(0xfe00000000000000);
 512         break;
 513
 514       case AlphaISA::IPR_EXC_SUM:
 515       case AlphaISA::IPR_EXC_MASK:
 516         // any write to this register clears it
 517         ipr[idx] = 0;
 518         break;
 519
 520       case AlphaISA::IPR_INTID:
 521       case AlphaISA::IPR_SL_RCV:
 522       case AlphaISA::IPR_MM_STAT:
 523       case AlphaISA::IPR_ITB_PTE_TEMP:
 524       case AlphaISA::IPR_DTB_PTE_TEMP:
 525         // read-only registers
 526         return new UnimplementedOpcodeFault;
 527
 528       case AlphaISA::IPR_HWINT_CLR:
 529       case AlphaISA::IPR_SL_XMIT:
 530       case AlphaISA::IPR_DC_FLUSH:
 531       case AlphaISA::IPR_IC_FLUSH:
 532         // the following are write only
 533         ipr[idx] = val;
 534         break;
 535
 536       case AlphaISA::IPR_DTB_IA:
 537         // really a control write
 538         ipr[idx] = 0;
 539
 540         dtb->flushAll();
 541         break;
 542
 543       case AlphaISA::IPR_DTB_IAP:
 544         // really a control write
 545         ipr[idx] = 0;
 546
 547         dtb->flushProcesses();
 548         break;
 549
 550       case AlphaISA::IPR_DTB_IS:
 551         // really a control write
 552         ipr[idx] = val;
 553
 554         dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
 555         break;
 556
 557       case AlphaISA::IPR_DTB_TAG: {
 558           struct AlphaISA::PTE pte;
 559
 560           // FIXME: granularity hints NYI...
 561           if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
 562               panic("PTE GH field != 0");
 563
 564           // write entire quad
 565           ipr[idx] = val;
 566
 567           // construct PTE for new entry
 568           pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
 569           pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
 570           pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
 571           pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
 572           pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
 573           pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
 574           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 575
 576           // insert new TAG/PTE value into data TLB
 577           dtb->insert(val, pte);
 578       }
 579         break;
 580
 581       case AlphaISA::IPR_ITB_PTE: {
 582           struct AlphaISA::PTE pte;
 583
 584           // FIXME: granularity hints NYI...
 585           if (ITB_PTE_GH(val) != 0)
 586               panic("PTE GH field != 0");
 587
 588           // write entire quad
 589           ipr[idx] = val;
 590
 591           // construct PTE for new entry
 592           pte.ppn = ITB_PTE_PPN(val);
 593           pte.xre = ITB_PTE_XRE(val);
 594           pte.xwe = 0;
 595           pte.fonr = ITB_PTE_FONR(val);
 596           pte.fonw = ITB_PTE_FONW(val);
 597           pte.asma = ITB_PTE_ASMA(val);
 598           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 599
 600           // insert new TAG/PTE value into data TLB
 601           itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
 602       }
 603         break;
 604
 605       case AlphaISA::IPR_ITB_IA:
 606         // really a control write
 607         ipr[idx] = 0;
 608
 609         itb->flushAll();
 610         break;
 611
 612       case AlphaISA::IPR_ITB_IAP:
 613         // really a control write
 614         ipr[idx] = 0;
 615
 616         itb->flushProcesses();
 617         break;
 618
 619       case AlphaISA::IPR_ITB_IS:
 620         // really a control write
 621         ipr[idx] = val;
 622
 623         itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
 624         break;
 625
 626       default:
 627         // invalid IPR
 628         return new UnimplementedOpcodeFault;
 629     }
 630
 631     // no error...
 632     return NoFault;
 633 }
 634
 635 /**
 636  * Check for special simulator handling of specific PAL calls.
 637  * If return value is false, actual PAL call will be suppressed.
 638  */
 639 bool
 640 ExecContext::simPalCheck(int palFunc)
 641 {
 642     kernelStats->callpal(palFunc);
 643
 644     switch (palFunc) {
 645       case PAL::halt:
 646         halt();
 647         if (--System::numSystemsRunning == 0)
 648             new SimExitEvent("all cpus halted");
 649         break;
 650
 651       case PAL::bpt:
 652       case PAL::bugchk:
 653         if (system->breakpoint())
 654             return false;
 655         break;
 656     }
 657
 658     return true;
 659 }
 660
 661 //Forward instantiation for FastCPU object
 662 template
 663 void AlphaISA::processInterrupts(FastCPU *xc);
 664
 665 //Forward instantiation for FastCPU object
 666 template
 667 void AlphaISA::zeroRegisters(FastCPU *xc);
 668
 669 #endif // FULL_SYSTEM